Hello,
I tried to change the FPGA design using the new (N2x0 rev3) as template
by simply letting the strobe and sample output of the dsp_core_rx1 open
and assigning them to fixed values:
----- (file: u2plus_core.v) ------------
dsp_core_rx #(.BASE(SR_RX_DSP1)) dsp_core_rx1
(.clk(dsp_clk),.rst(dsp_rst),.set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
.adc_i(adc_i),.adc_ovf_i(adc_ovf_a),.adc_q(adc_q),.adc_ovf_q(adc_ovf_b),.sample(
), .run(run_rx1_d1), .strobe( ), .debug() );
assign sample_rx1 = 32'hDEAD_BEEF;
assign strobe_rx1 = 1;
----
But it looks like this is taking hours (~2hrs) to compile the FPGA
design (especially Place and Route is taking really long). (I'm using
xilinx ise 13.1)
When I used the original design (with strobe_rx1 and sample_rx1 attached
to the dsp_core_rx1) it compiled much much faster.
After I finally got the output bin file I burned it into the SPI flash
and the device booted fine. Then in GRC I tried to attach both channels
to a File Sink using the USRP subdev specification you suggested me
(thank you for that). It looks like nothing is coming out of both
channels the sink output filesize remains zero bytes.
Is there maybe anything i have overlooked when I was changing the FPGA
design?
Best Regards,
Eral
On 14/09/2011 04:04, Josh Blum wrote:
On 09/13/2011 07:48 AM, Eral Tuerkyilmaz wrote:
Hello,
Thanks for your suggestion. I tried to replace the second DSP Core by a
simple counter so that i should receive something on the second channel.
Then instatiated a UHD source block in GRC, added a second channel (Num
Channels = 2) to the UHD Source block and configured it the same way as
the other channel. Then I tried to run the graph but it keeps telling me
that the configuration of the the second channel is wrong (e.g:
uhd_usrp_source_0.set_center_freq(10000000, 1) leads to
vector::_M_range_check ... Maybe I'm just using wrong parameters for the
second channel?)
Yea, it needs a subdev spec to map the wbx frontend to DSP0 and DSP1,
try "A:0 A:0" for the string representation.
-josh
By the way: I'm using a WBX board to get the I/Q Samples. Are there
maybe any other parameters for the USRP board necessary (subdev specs?)
to get this additional samples?
Thank you,
Eral
On 05/09/2011 09:55, Josh Blum wrote:
You may want to replace the second DSP in the top level verilog with
your own module. On the host side, just configure the uhd source block
for two channels.
On 09/04/2011 11:18 PM, Eral Tuerkyilmaz wrote:
Hi,
I want to change my USRP N210 - FPGA config to calculate a correlation
sum and transmit this sum synchronously with the I/Q sample pairs to the
PC (e.g to get this samples from an extra channel on the UHD block).
What would be the easiest way to transmit these additional data to the
samples and where are changes necessary (firmware, fpga-config)?
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