Hello,

Thanks for your suggestion. I tried to replace the second DSP Core by a
simple counter so that i should receive something on the second channel.

Then instatiated a UHD source block in GRC, added a second channel (Num
Channels = 2) to the UHD Source block and configured it the same way as
the other channel. Then I tried to run the graph but it keeps telling me
that the configuration of the the second channel is wrong (e.g:
uhd_usrp_source_0.set_center_freq(10000000, 1) leads to
vector::_M_range_check ... Maybe I'm just using wrong parameters for the
second channel?)


By the way: I'm using a WBX board to get the I/Q Samples. Are there
maybe any other parameters for the USRP board necessary (subdev specs?)
to get this additional samples?

Thank you,
Eral

On 05/09/2011 09:55, Josh Blum wrote:


You may want to replace the second DSP in the top level verilog with
your own module. On the host side, just configure the uhd source block
for two channels.


> On 09/04/2011 11:18 PM, Eral Tuerkyilmaz wrote:
>> Hi,
>>
>> I want to change my USRP N210 - FPGA config to calculate a correlation
>> sum and transmit this sum synchronously with the I/Q sample pairs to the
>> PC (e.g to get this samples from an extra channel on the UHD block).
>> What would be the easiest way to transmit these additional data to the
>> samples and where are changes necessary (firmware, fpga-config)?
>>




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