Thanks, Josh! Then we will find a Xilinx ISE and see what's the next step.
Yooxi Josh Blum-3 wrote: > > > > On 08/24/2011 09:30 PM, xi yang wrote: >> Hi, all, >> >> We have made a FPGA FFT module. >> We downloaded the UHD source code from >> https://github.com/EttusResearch/UHD-Mirror/archives/master >> We modified the usrp_std.v under >> fpga/usrp1/toplevel/usrp_std/ >> to link our FFT module between rx_buffer and USB. >> We have successfully compiled the usrp_std.qpf in Quartus II 9.1. >> How can we make it effective in our USRP E100? > > You build images for the USRP1. That is a different product than E100. > > Pre-built images are here: > http://code.ettus.com/redmine/ettus/projects/uhd/wiki#Binary-downloads > > Installation notes: > http://ettus.dyndns.org/uhd_docs/manual/html/images.html#archive-install > > The verilog source can be found here: > http://code.ettus.com/redmine/ettus/projects/uhd/repository/revisions/master/show/fpga/usrp2/top/E1x0 > > -josh > > _______________________________________________ > Discuss-gnuradio mailing list > Discuss-gnuradio@gnu.org > https://lists.gnu.org/mailman/listinfo/discuss-gnuradio > > -- View this message in context: http://old.nabble.com/How-to-update-FPGA-in-E100-tp32331437p32338234.html Sent from the GnuRadio mailing list archive at Nabble.com. _______________________________________________ Discuss-gnuradio mailing list Discuss-gnuradio@gnu.org https://lists.gnu.org/mailman/listinfo/discuss-gnuradio
