> Thanks a lot for your help. Could you explain how to slow down the FPGA/ADC > rate? How should we modify the firmware? Which part of the code should we > look into? Thanks! > >
This is a host code modification. see the clock_ctrl.cpp in host/lib/usrp/usrp_e100/ http://code.ettus.com/redmine/ettus/projects/uhd/repository/revisions/master/entry/host/lib/usrp/usrp_e100/clock_ctrl.cpp You will want to manipulate codec clock. -Josh _______________________________________________ Discuss-gnuradio mailing list Discuss-gnuradio@gnu.org http://lists.gnu.org/mailman/listinfo/discuss-gnuradio
