As far as I know, the decimation is after the ADC, so ADC rate doesn't change
after changing the clock rate.  I'm happy to be corrected if it's not so. :)



That's correct. The ADC rates are fixed across all the products. That vastly simplifies things both in the FPGA
  DDC+CIC decimators, and the analog interface in front of the ADC.



--
Marcus Leech
Principal Investigator
Shirleys Bay Radio Astronomy Consortium
http://www.sbrac.org



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