On 12.01.2011 20:22, Marcus D. Leech wrote:
If connected to a Xilinx board, FIR and decimation could still be done in the
FPGA.
Agreed.
There's a cheap one here, with USB2 and Spartan3, only 70€ (<$100)
http://www.ztex.de/usb-fpga-1/usb-fpga-1.2.d.html
Or this one for 145€?
http://www.cesys.com/fpga/spartan/efm01_en.html
Do you think the FMC interface can be realized with the 52 Xilinx GPIO pins,
just with the specific FMC driver software?
Quite possibly, don't actually know that much about FMC, but my
impression is that it's a fairly-generic way of
putting expansion "goop" onto a generic FPGA board.
Is this really a problem? For spectral analysis this is only an axis shift.
For demodulation you would have to do some kind of adaptive doppler
compensation and phase
tracking anyway. Could all this be done by continuously changing the DDC
parameters over the wire?
Maybe, maybe not. Depends on the applications, but I'm guessing that a
significant number of applications can
get away with the fact that their signal of interest isn't exactly at
DC, and do the DDC in software.
For example, I happen to be interested in signals centered at
1420.40575Mhz. But I'd be perfectly happy
if the "0Hz" in the signals was actually at 1420.400MHz--I could
compensate in the software side. Resolution
of 50KHz or better should be achievable with the PLL I've shown on
the block diagram. Phase noise improves
with larger resolutions, however.
--
Marcus Leech
Principal Investigator
Shirleys Bay Radio Astronomy Consortium
http://www.sbrac.org
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