On Wed, Jan 12, 2011 at 3:31 PM, Gabriel Morel <morelgabr...@videotron.ca> wrote: > If you don't trust me, try it. Use Xilinx on Windows, create a project and > put in all file of all different makefile in the repo for USRP2 with > u2_rev3.v in top. Implement top module and create the bin file. After, > give me some news plz. It's not loosing time, nobody had answer to my > question and somebody have same problem than me. Thx a lot. > > Gab
Instead of creating a new project, have you tried simply using the supplied Makefile and calling make from cygwin instead? I have never tried building the image from a Windows install of Xilinx - but in general the supplied makefile gives Xilinx the correct optimization/etc. settings to ensure the build works correctly. I'll note that while the instructions on http://www.ettus.com/uhd_docs/manual/html/images.html may not be exactly step by step, they do lay out that the build environment uses make, and in which directories the corresponding Makefiles can be found. Examining them will likely be very helpful if you wish to make modifications to the FPGA image - just as understanding the complete build environment will be just as important as Verilog/VHDL coding skills. I have never found that trying to re-create the project in the Xilinx GUI to be at all useful as far as getting working hardware is concerned. Doug -- Doug Geiger doug.gei...@bioradiation.net _______________________________________________ Discuss-gnuradio mailing list Discuss-gnuradio@gnu.org http://lists.gnu.org/mailman/listinfo/discuss-gnuradio
