Matt,
Ok, I will compile the raw ethernet project for the USRP2 to be sure
that I can modify it and use the modified version to my master. I was
try to compile the project fpga.git under ISE10.1 and under ISE12.1.
The two method compile well, give two different size of binary file,
but both don't work in the USRP2.
From my indirect experience on a non-GnuRadio Xilinx FPGA project,
there's a bit of a black art to getting apparently-semantically-good
Verilog from the "it compiles", "it passes timing", "the simulations
are good", to actually working on real hardware. Different versions of
the tools use different optimization and placement strategies that
can easily result in a piece of code that "looks good" simply not
mapping onto hardware in a way that will work.
If the software development process worked as poorly as the
Verilog+real-hardware+vendor-blackmagic-tools apparently does, I'd
leave software and take up basket weaving. I admit to having a
certain admiration for the folks in the FPGA/Verilog world who
can stomach the apparent capriciousness of it, and persevere and
produce working hardware. Not for the faint of heart.
--
Marcus Leech
Principal Investigator
Shirleys Bay Radio Astronomy Consortium
http://www.sbrac.org
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