On 08/12/2010 06:22 AM, Cheaw Wen Guey wrote:
Hi all,
As per the advice given, I have started to try change the FPGA code to
bypass the DDC for the USRP2.
I am first trying to edit using the 30day trial for ISE v12 in Windows.
I have 2 questions,
1. I fail to locate the project file from the git.
The project file is generated by a tcl script
http://www.ettus.com/uhd_docs/manual/html/usrp2.html#building-firmware-and-fpga-images
On windows, you will need make (probably gnu make), and the xilinx
xtclsh (xilinx tcl shell) in your path. I would use cygwin.
2. I was wondering if the AeMB processor directly feeds off the output of
the DDC module (i_out and q_out) or it only manages the flow of data?
The microblaze manages the flow of data by acting as a packet router. In
firmware/microblaze/lib/ see dbsm.*
-Josh
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