Hi all,

As per the advice given, I have started to try change the FPGA code to
bypass the DDC for the USRP2.

I am first trying to edit using the 30day trial for ISE v12 in Windows.

I have 2 questions,

1. I fail to locate the project file from the git.

2. I was wondering if the AeMB processor directly feeds off the output of
the DDC module (i_out and q_out) or it only manages the flow of data?

thanks in advance


Cheaw Wen Guey
Research Officer


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