On 05/21/2010 09:33 AM, Harley Myler wrote: > I traced those from the WBX simple GDB, through the WBX and to the USRP2. > They wind-up at U1 (XC3SXX00FG456−IO7(tx)) and U1 (XC3SXX00FG456−IO2(rx)) on > page 3 of 8 of the USRP2 schematic. I do not know why they are both labelled > "U1". The date, revision and drawn-by blocks only had tokens. I may be > looking at a preliminary schematic. > It's pretty standard industry practice to "break up" many-pinned chips on the schematic into functional units, but they still get labelled with the same part number, because in reality it's all the same part.
We do that at two of the companies I work for, and I've seen it in lots of other schematics as well. > So at this juncture my assumption is that the FPGA(s) given by the XC... > labels above, although I cannot find a Xylinx part number match, simply run > out to the 20 pin header connector on the daughterboard. Of the sixteen > lines, each daughterboard usurps--an ironic term here--any number of the > available 16 GPIOs for their own purposes and what is left are available to > the user. > > As such, my conclusion is that the following, per the schematic, are > available: > > RX Control Pins io_rx[15:14] −− Unused > TX Control Pins iotx[15:8] −− Unused > > This gives 9 GPIO pins available to the user, hardly 16. The product > documentation should reflect this. Nevertheless, nine will be adequate for my > purposes. > > I count ten (10). -- Marcus Leech Principal Investigator Shirleys Bay Radio Astronomy Consortium http://www.sbrac.org _______________________________________________ Discuss-gnuradio mailing list Discuss-gnuradio@gnu.org http://lists.gnu.org/mailman/listinfo/discuss-gnuradio
