On Tue, Apr 8, 2008 at 1:01 PM, Firas Abbas <[EMAIL PROTECTED]> wrote:
> Hi,
>
> If the I,Q bit width output of the DDC is reduced from 16 bit to 12 bit,
> then I & Q will occupy 24 bit (3 Bytes). Thus we will be able to maximize
> the instantaneous bandwidth to 32MB/3 = 10.6MHz without scarifying much
> because the original signal was digitized with 12 bit ADC.

In theory down-sampling should be reducing the noise floor below the
initial 12 bit level though... so there should be some loss in dynamic
range.


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