Hi, If the I,Q bit width output of the DDC is reduced from 16 bit to 12 bit, then I & Q will occupy 24 bit (3 Bytes). Thus we will be able to maximize the instantaneous bandwidth to 32MB/3 = 10.6MHz without scarifying much because the original signal was digitized with 12 bit ADC.
Regards, Firas Paul Creekmore <[EMAIL PROTECTED]> wrote: Tyrel, The current FPGA configuration does not support 4-bit samples, but it is possible to modify the configuration (Verilog code) to convert the samples to 4-bit. My research group is currently working on adding 1, 2, and 4-bit quantization options to the USRP, as well as accompanying data packing to maximize the number of samples that we can squeeze across the USB interface and thus also the receivable signal bandwidth. We've not yet tested the modifications. --Paul Tyrel Newton wrote: <div class="moz-text-flowed" style="font-family: -moz-fixed">We have an application where the overall accuracy of the A/D converter is not terribly important but where we need as high a sampling rate as we can get. To this end, we found and intend to use the 8-bit option that allows for 8-bit I and Q signals instead of the normal 16-bit. However, is there a similar option that allows for 4-bit I and Q samples? Or similarly, would it be relatively easy to implement a 4-bits per sample scheme, possibly w/ slight modifications to the USRP firmware? Any feedback and/or advice is greatly appreciated. Regards, Tyrel </div> _______________________________________________ Discuss-gnuradio mailing list Discuss-gnuradio@gnu.org http://lists.gnu.org/mailman/listinfo/discuss-gnuradio
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