Brian Padalino wrote:
You have to think about what this is trying to accomplish. Everything in the Verilog code is 0 based array indexing. That answers question #1. Question #2 is answered by understanding what the actual statement is accomplishing:
*check*
For every received sample strobe, go through all the channels and, as long as the received FIFO is not full, pass the data. In Verilog, this is accomplished in the next couple of clock cycles until it iterates through all the channels. Does that make sense?
Yes, it does now. I suppose I didn't know RX strobe was the sample strobe. :) I definitely need my FIFO write request to reflect store_next being 0 then. Cool, I'm starting to understand some of this!
- George _______________________________________________ Discuss-gnuradio mailing list Discuss-gnuradio@gnu.org http://lists.gnu.org/mailman/listinfo/discuss-gnuradio
