Brian Padalino wrote:
Looking at the flow, each channel has a fifo1kx16 each, which you are
presumably going to make a fifo512x32?
I have a feeling you're going to have to modify your packet_builder as
well. The packet_builder looks at the channel FIFOs sequentially and
builds a packet based on that FIFO. You need to add a state or some
extra logic in the FORWARD state that will FORWARD_I then FORWARD_Q
from the input chan_fifodata.
That seems to be the only place where it's used, so if you make your
interface 32 bits instead of 16, and make the change to the FSM, you
should be interleaving happily.
Good luck with your modification.
Taking a look at how the legacy code does it...
http://gnuradio.org/trac/browser/gnuradio/branches/developers/gnychis/inband/usrp/fpga/sdr_lib/rx_buffer.v#L137
What do you think about adopting this method? It's using a 16-bit wide
FIFO still and just alternating between which channel it is feeding in
to the FIFO using a channel counter (store_next). In our case, we would
just alternate between channel 0 and channel 1 to have 1 full data
channel, for now. Unless there is something different in our case that
I'm unaware of. This would prevent us from having to change the
megacells and re-write some of the other state machines.
- George
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