From some discussion on comp.dsp, it seems as though I'm looking for a
matched filter:
http://groups.google.com/group/comp.dsp/browse_thread/thread/f93d7867f74dbe95#0dc48f2a8ed09e07
If you see what I'm getting at, if I implement a matched filter in the
FPGA (given that it does what I think it does ;)), I can detect incoming
frames without using the PHY layer.
Let's say that a simple requirement is this: the frame format must have
the destination address directly after the framing sequence. Therefore
I could use the matched filter to detect incoming frames to my address
in the FPGA using a single sequence, without the turnaround time to the
host.
By doing this, I could generate ACKs much faster by storing
pre-modulated data in the FPGA which is triggered.
- George
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