On 6/16/07, John Kent <[EMAIL PROTECTED]> wrote:
Are they using a NIOS processor for the USB interface by any chance ?
No, a Cypress FX2 is used for the USB MAC/PHY. I believe the next design is going to have an opencores processor within it.
It sounds like the Altera device more closely resembles the Spartan 2. I have not played with the SRL16 blocks, but it sounds like I should read up on them.
SRL16 information can be seen here: http://toolbox.xilinx.com/docsan/xilinx5/data/docs/lib/lib0393_377.html For a signal processing prospective, Xilinx has an app note about writing a CDMA matched filter here: http://www.xilinx.com/bvdocs/appnotes/xapp212.pdf
All the FPGA code I have written so far has been in VHDL rather than Verilog. I'm not sure there is really a big difference.
VHDL is based on ADA and is strongly typed. VHDL also has more support for configurations, generate loops, etc. Verilog is a bit more loose and not as high level. I, too, do most of my work in VHDL but have some experience within Verilog.
We had a talk at the North East Radio Group a couple of years ago on digital TV and the guy there talked about encoding the video stream on 1024 separate carriers. It might have been for a repeater system transmitting on the same frequency though. I'm a bit hazy on the details.
The digital video standard in the United States uses 8-VSB for the modulation scheme, whereas the rest of the world seems to have settled on using an OFDM solution. What you are describing there sounds very much like an OFDM implementation. There is currently an effort underway for getting OFDM working on the USRP. Brian _______________________________________________ Discuss-gnuradio mailing list Discuss-gnuradio@gnu.org http://lists.gnu.org/mailman/listinfo/discuss-gnuradio
