On Fri, Apr 20, 2007 at 08:26:25PM +0200, Anmar wrote: > Eric Blossom wrote: > > On Wed, Apr 18, 2007 at 01:49:36PM +0200, Anmar wrote: > > > > You can control the phase in the FPGA. However, we're using the > > digital upconverter in the AD9862. That DUC has its own phase > > register. > > Loading the code below, I connected the two daughterboard’s to the X and > Y channel of the scoop. every time I load the code I get a different > angel on the scoop(but there is a constant change with it). how can I > explain why this is happening?
OK, here goes, one more time: there is state in the AD9862 -- its DUC phase register -- that we can't control from software. Do you understand what that means? Have you looked at the AD9862 data sheet? If you cycle power on the USRP _each time_ before you run the experiment, do you get repeatable results? What daughterboards are you using? Have you read and understood http://gnuradio.org/trac/wiki/USRPClockingNotes ??? > def main(): > interp = 128 > waveform_type = gr.GR_COS_WAVE > waveform_ampl = 16000 > waveform_freq1 = 40e3 > waveform_freq2 = 10e3 > waveform_offset = 0 > fg = gr.flow_graph () > sink = usrp.sink_c (0, interp) > sink.set_nchannels(2) > sink.set_mux(0xba98) > usb_freq = sink.dac_freq() / interp > siggen1 = gr.sig_source_c (usb_freq, > gr.GR_SIN_WAVE, > waveform_freq1, > waveform_ampl, > waveform_offset) > > siggen2 = gr.sig_source_c (usb_freq, > gr.GR_SIN_WAVE, > waveform_freq2, > waveform_ampl, > waveform_offset) > > inter = gr.interleave(gr.sizeof_gr_complex) > fg.connect (siggen1, (inter, 0)) > fg.connect (siggen2, (inter, 1)) > fg.connect (inter, sink) > fg.start() > raw_input('Press enter to stop\n') > fg.stop() > > if __name__ == '__main__': > main() > > thanks > anmar _______________________________________________ Discuss-gnuradio mailing list Discuss-gnuradio@gnu.org http://lists.gnu.org/mailman/listinfo/discuss-gnuradio
