On 11/10/06, Eric Blossom <[EMAIL PROTECTED]> wrote:
Yes, I could enable the output pins from the host and just connect the rx_a_a to one of the debug inputs in the master_control module. I thaught it wouldn't make a difference if I just connect it directly to the DEBUG pins. Or does it?
No antenna is connected to the RX-A and RX-B ports , so those are floating. But the debug pins are connected to the logic analyzer. (I am not sure if I answered you're question, when you say "they" are you referring to the DEBUG pins or the input ports? )
Ok. Thanks for the suggestion. I will try that and see what I get.
Oussama.
On Fri, Nov 10, 2006 at 06:01:02PM -0800, Oussama Sekkat wrote:
> Hi,
>
> I'm trying to use my logic analyzer to measure the received noise.
> Here is how I proceed to do that. First in the verilog code, I connect the
> 12 bit rx_a_a ADC input to the io_rx_a DEBUG output by adding this line of
> code:
> assign io_rx_a = {4'b0000, rx_a_a }
A much less invasive way to handle this would have been to take
advantage of the support for sending whatever debug values you want to
the i/o pins by using the debug_0,..., debug_3 parameters of the
master_control block. See also the FR_DEBUG_EN register documented
in fpga_regs_common.{h,v}
// If the corresponding bit is set, internal FPGA debug circuitry
// controls the i/o pins for the associated bank of daughterboard
// i/o pins. Typically used for debugging FPGA designs.
#define FR_DEBUG_EN 14
# define bmFR_DEBUG_EN_TX_A (1 << 0) // debug controls TX_A i/o
# define bmFR_DEBUG_EN_RX_A (1 << 1) // debug controls RX_A i/o
# define bmFR_DEBUG_EN_TX_B (1 << 2) // debug controls TX_B i/o
# define bmFR_DEBUG_EN_RX_B (1 << 3) // debug controls RX_B i/o
Yes, I could enable the output pins from the host and just connect the rx_a_a to one of the debug inputs in the master_control module. I thaught it wouldn't make a difference if I just connect it directly to the DEBUG pins. Or does it?
> I then load the .rbf file to the FPGA, connect the io_rx_a outputs of the
> LFRX daughter board to the logic analyzer and observe what I get. I make
> sure that no antenna is connected to the RX-A port.
> To my surprise, some of the upper bits toggle. For example, bit 11, 10, 9,
> 8, 5 ,4 , 3 ,2 ,1 0, toggle. Since I should only be getting noise, I was
> expecting to get a very low signal where only the least significant bit
> would be switiching between low and high values.
Are they being driven or are they just floating?
No antenna is connected to the RX-A and RX-B ports , so those are floating. But the debug pins are connected to the logic analyzer. (I am not sure if I answered you're question, when you say "they" are you referring to the DEBUG pins or the input ports? )
My guess is that they are floating.
My suggestion (once again) is to use some of debug_0,... debug_3,
write to FR_DEBUG_EN and then enable the outputs of the particular
pins using u._write_oe(which, value, mask)
Ok. Thanks for the suggestion. I will try that and see what I get.
Oussama.
> Does anyone know what could be the origin of such results? Any insight would
> be greatly appreciated.
>
> Thank you,
>
> Oussama.
Eric
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