On 11/17/06, Eric Blossom <[EMAIL PROTECTED]> wrote:
On Fri, Nov 17, 2006 at 07:13:05PM -0800, Oussama Sekkat wrote: > Hi, > > I am still trying to measure the digital output noise (from the LFRX_A > daughterboard). > In the verilog code I made sure to connect the rx_a_a input to the debug1 > input of the master control module > master_control master_control > ( .master_clk(clk64),.usbclk(usbclk) ....... > ............ .debug_1(rx_a_a),.debug_0(ddc0_in_i)........); > > then my python code looks like the following: > > u = usrp.sink_c(0, 64, fpga_filename="usrp_test.rbf") > side = 0 # side A > u._write_oe(side, 0xffff, 0xffff) # set all i/o pins as outputs > u._write_fpga_reg(FR_DEBUG_EN, bmFR_DEBUG_EN_RX_A) > > I then connect the io_rx debug outputs of side A to the logic analyzer. (no > antenna is inserted) > I was expecting to get some noise , but I get a 0 signal ( 16 bit zeroes :( > ) > > Any ideas on why this is happening? Any suggestions? > > Thank you ahead of time. > > Oussama You have opened the Tx side (the sink), and output enabled the pins on the side A Tx daughterboard. Then you've connected your logic analyzer to the side A Rx daughterboard. Those pins are not output enabled.
Ok. I fixed it now by making it a source instead. Thanks. My output reading from the logic analyzer is now the following constant 16 bit value: 0000 1111 1100 0011 This seems to me a too high of a value since I shouldn't be receiving any signal. On top of that, none of the bits are toggling, which doesn't make sense if it was just noise. Any ideas on what's going on here? Thanks again, Oussama. Eric
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