On Wed, Feb 22, 2006 at 11:32:38AM -0500, amit malani wrote: > did u updated only the .v and .rbf files or complete project as well?
Generally the project file is pretty static. Note that you don't have to build the .rbf's from source. We distribute pre-compiled versions in the usrp/fpga/rbf directory. > also, I could not understand the heirarchy of the files. i mean the verilog > files. which all are included for the final synthesis? is fullchip, > the toplevel entity, the one that includes every thing? > i tried to the run the project in usrp/fpga/toplevel/fullchip... the > fullchip.qpf it gave me a notification that the project is made with > older version of quartus. I've added some commentary to the usrp/README: # Compiling the verilog (not required unless you're modifying it) To build the fpga configuration bitstring you'll need Altera's no cost Quartus II development tools. We're currently building with Quartus II 5.1sp1 Web Edition. The project file is usrp/fpga/toplevel/usrp_std/usrp_std.qpf. The toplevel verilog file is usrp/fpga/toplevel/usrp_std/usrp_std.v. The bulk of the verilog modules are contained in usrp/fpga/sdr_lib. Hope this helps! Eric _______________________________________________ Discuss-gnuradio mailing list Discuss-gnuradio@gnu.org http://lists.gnu.org/mailman/listinfo/discuss-gnuradio
