> Who are the lead developers of KiCAD who take that decision? I think already > KiCAD might be able to do this thing. The only thing not implemented is that > of exporting an edif file.
As usual in OpenSource, if you are interested in features to be implemented, then coming up with a detailed list of features to discuss on the list, then putting them on the issue/feature-request tracker, followed by pull requests by you or people you can got interested in the process is the best way to arrive at the features you are interested in. The Lead developers will guide you through the process with the right questions and will point out suggestions or concerns. And they will be helping in the code reviews, but it is ultimately _you_ who will end up being the lead developer for this feature-set as you will make it happen. Cheers, -h > Thanking you > Sagar Acharya > https://designman.org > > > > 22 Apr 2023, 17:39 by stambau...@gmail.com: > > > Hi Sagar, > > > > There is definitely interest in including chip design capability in KiCad, > > when that happens really depends on a lot of factors. I'm not familiar > > with the code listed below, but a good start to getting a feature like this > > into KiCad would be to ensure all of the code in the list below is packaged > > for all the platforms supported by KiCad[1]. Once that hurdle is cleared, > > we would need to write a design document about how we would integrate > > support for chip design into KiCad. After the lead development team agrees > > on the design document, then we could actually start any implementation as > > manpower becomes available. > > > > Cheers, > > > > Wayne > > > > [1]: https://www.kicad.org/help/system-requirements/ > > > > On 4/19/23 2:24 PM, 'Sagar Acharya' via KiCad Developers wrote: > > > >> For this purpose in free software, there are a few softwares like > >> > >> magic VLSI & > >> gdspy & > >> gdstk & > >> skywater-pdk > >> Thanking you > >> Sagar Acharya > >> https://designman.org > >> > >> > >> > >> 19 Apr 2023, 23:51 by sagaracha...@tutanota.com: > >> > >>> Respected devs, > >>> > >>> I was exploring into chip designs and except the aspects of automation of > >>> placement and routing and testing for logic, at the end, semiconductor > >>> chip design is extremely similar to designing a board. > >>> > >>> It consists of a bunch of blocks for different Si layers, oxide layers, > >>> metal layers, etc. which in my view is already supported in kicad. If the > >>> grid size is set to be of order of lambda, a parameter in chip design, > >>> say like 40nm, an output of oasis file/edif file can result in a complete > >>> EDA. > >>> > >>> I welcome your thoughts on this. > >>> > >>> Thanking you > >>> Sagar Acharya > >>> https://designman.org > >>> > > > > -- > > You received this message because you are subscribed to the Google Groups > > "KiCad Developers" group. > > To unsubscribe from this group and stop receiving emails from it, send an > > email to devlist+unsubscr...@kicad.org. > > To view this discussion on the web visit > > https://groups.google.com/a/kicad.org/d/msgid/devlist/823381a9-cccf-a15d-8fe3-08514016b98c%40gmail.com. > > > > -- > You received this message because you are subscribed to the Google Groups > "KiCad Developers" group. > To unsubscribe from this group and stop receiving emails from it, send an > email to devlist+unsubscr...@kicad.org. > To view this discussion on the web visit > https://groups.google.com/a/kicad.org/d/msgid/devlist/NTiWi5Z--3-9%40tutanota.com. -- You received this message because you are subscribed to the Google Groups "KiCad Developers" group. To unsubscribe from this group and stop receiving emails from it, send an email to devlist+unsubscr...@kicad.org. To view this discussion on the web visit https://groups.google.com/a/kicad.org/d/msgid/devlist/CAEQqtJwKbdSfCcAjJeeH-qML2DZR6mXpT_k3S_5XycisXCSd6g%40mail.gmail.com.
