This is far out of scope for what KiCad is intended for and would quickly be broken many times over as we don't have manpower or interest to maintain it.
It's a lot more work than you make it seem to get it correct and there'll be demands to add more and more. Maybe 10 years from now when the board design feature set is actually complete ;) On Wed, Apr 19, 2023 at 2:21 PM 'Sagar Acharya' via KiCad Developers <devlist@kicad.org> wrote: > > Respected devs, > > I was exploring into chip designs and except the aspects of automation of > placement and routing and testing for logic, at the end, semiconductor chip > design is extremely similar to designing a board. > > It consists of a bunch of blocks for different Si layers, oxide layers, metal > layers, etc. which in my view is already supported in kicad. If the grid size > is set to be of order of lambda, a parameter in chip design, say like 40nm, > an output of oasis file/edif file can result in a complete EDA. > > I welcome your thoughts on this. > Thanking you > Sagar Acharya > https://designman.org > > -- > You received this message because you are subscribed to the Google Groups > "KiCad Developers" group. > To unsubscribe from this group and stop receiving emails from it, send an > email to devlist+unsubscr...@kicad.org. > To view this discussion on the web visit > https://groups.google.com/a/kicad.org/d/msgid/devlist/NTPk3-T--3-9%40tutanota.com. -- Mark -- You received this message because you are subscribed to the Google Groups "KiCad Developers" group. To unsubscribe from this group and stop receiving emails from it, send an email to devlist+unsubscr...@kicad.org. To view this discussion on the web visit https://groups.google.com/a/kicad.org/d/msgid/devlist/CAJjB1q%2B5SoQnc2%2BnSNxHifWpBhGKS7b04qoMaG1P6vMpT1LuMg%40mail.gmail.com.
