[AMD Official Use Only - AMD Internal Distribution Only]
Hi Mike, Liming and Zhiguang,
Could you please check this patch sent two weeks ago? The corresponding BZ
ticket is 4775. We overlooked tracking this issue and missed the 202405 stable
release. As this impacts the build, do you think we can have a quick review and
approve it; having this change pulled in 202405 stable release? Otherwise we
will have to wait until next stable release.
Thanks
Abner
> -----Original Message-----
> From: Hsueh, Hong-Chih (Neo) <hong-chih.hs...@amd.com>
> Sent: Thursday, May 2, 2024 3:31 AM
> To: devel@edk2.groups.io
> Cc: michael.d.kin...@intel.com; gaolim...@byosoft.com.cn;
> zhiguang....@intel.com; He, Jiangang <jiangang...@amd.com>; Chang,
> Abner <abner.ch...@amd.com>; Hsueh, Hong-Chih (Neo) <Hong-
> chih.hs...@amd.com>
> Subject: [PATCH] MdePkg: Remove non-ASCII characters from header file
>
> Cc: Jiangang He <jiangang...@amd.com>
> Signed-off-by: Neo Hsueh <hong-chih.hs...@amd.com>
> ---
> MdePkg/Include/Register/Amd/Cpuid.h | 4 ++--
> MdePkg/Include/Register/Intel/ArchitecturalMsr.h | 8 ++++----
> 2 files changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/MdePkg/Include/Register/Amd/Cpuid.h
> b/MdePkg/Include/Register/Amd/Cpuid.h
> index add43c40aa..51fa9f235c 100644
> --- a/MdePkg/Include/Register/Amd/Cpuid.h
> +++ b/MdePkg/Include/Register/Amd/Cpuid.h
> @@ -46,9 +46,9 @@ CPUID Signature Information
> CPUID Extended Topology Enumeration
>
> @note
> - Reference: AMD64 Architecture Programmer’s Manual Volume 3: General-
> Purpose and System Instructions,
> + Reference: AMD64 Architecture Programmer's Manual Volume 3: General-
> Purpose and System Instructions,
> Revision 3.35 Appendix E,
> - E.4.24 Function 8000_0026—Extended CPU Topology:
> + E.4.24 Function 8000_0026-Extended CPU Topology:
> CPUID Fn8000_0026 reports extended topology information for logical
> processors, including
> asymmetric and heterogenous topology descriptions. Individual logical
> processors may report
> different values in systems with asynchronous and heterogeneous
> topologies.
> diff --git a/MdePkg/Include/Register/Intel/ArchitecturalMsr.h
> b/MdePkg/Include/Register/Intel/ArchitecturalMsr.h
> index 756e7c86ec..4715c59dc4 100644
> --- a/MdePkg/Include/Register/Intel/ArchitecturalMsr.h
> +++ b/MdePkg/Include/Register/Intel/ArchitecturalMsr.h
> @@ -5733,9 +5733,9 @@ typedef union {
> /// [Bit 7:4] TME Policy/Encryption Algorithm: Only algorithms enumerated
> in
> /// IA32_TME_CAPABILITY are allowed.
> /// For example:
> - /// 0000 – AES-XTS-128.
> - /// 0001 – AES-XTS-128 with integrity.
> - /// 0010 – AES-XTS-256.
> + /// 0000 - AES-XTS-128.
> + /// 0001 - AES-XTS-128 with integrity.
> + /// 0010 - AES-XTS-256.
> /// Other values are invalid.
> ///
> UINT32 TmePolicy : 4;
> @@ -5756,7 +5756,7 @@ typedef union {
> /// Similar to enumeration, this is an encoded value.
> /// Writing a value greater than MK_TME_MAX_KEYID_BITS will result in
> #GP.
> /// Writing a non-zero value to this field will #GP if bit 1 of EAX
> (Hardware
> - /// Encryption Enable) is not also set to ‘1, as encryption hardware
> must be
> + /// Encryption Enable) is not also set to 1, as encryption hardware must
> be
> /// enabled to use MKTME.
> /// Example: To support 255 keys, this field would be set to a value of
> 8.
> ///
> --
> 2.40.0.windows.1
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