This happens to transfer PEI control to DXE. The paging is created for DXE phase, so, here, it's means the cpu running in the ia32 pei. I will refine the comments as below:
If cpu has already runned in X64 PEI, Page table Level in DXE must align with previous level. If cpu runs in IA32 PEI, Page table Level in DXE is decided by PCD and feature capbility. Thanks, Jiaxin > -----Original Message----- > From: Gerd Hoffmann <kra...@redhat.com> > Sent: Tuesday, May 9, 2023 10:44 PM > To: devel@edk2.groups.io; Wu, Jiaxin <jiaxin...@intel.com> > Cc: Bi, Dandan <dandan...@intel.com>; Gao, Liming > <gaolim...@byosoft.com.cn>; Dong, Eric <eric.d...@intel.com>; Ni, Ray > <ray...@intel.com>; Zeng, Star <star.z...@intel.com>; Kumar, Rahul R > <rahul.r.ku...@intel.com> > Subject: Re: [edk2-devel] [PATCH v1 3/3] MdeModulePkg/DxeIpl: Align Page > table Level setting with previous level. > > > + // > > + // If IA32, Page table Level is decided by PCD and feature capbility. > > + // > > There is neither 5-level nor 4-level paging support in ia32 mode. > > take care, > Gerd -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#104462): https://edk2.groups.io/g/devel/message/104462 Mute This Topic: https://groups.io/mt/98780503/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
