Jiaxin,
SDM has following:
> 3.3.7.1 Canonical Addressing
> In 64-bit mode, an address is considered to be in canonical form if **address
> bits 63 through to the most-significant implemented bit by the
> microarchitecture are set to either all ones or all zeros**.
> Intel 64 architecture defines a 64-bit linear address. Implementations can
> support less. The first implementation of IA-32 processors with Intel 64
> architecture supports a 48-bit linear address. This means a canonical address
> must have bits 63 through 48 set to zeros or ones (depending on whether bit
> 47 is a zero or one).
> Although implementations may not use all 64 bits of the linear address, they
> should check bits 63 through the most-significant implemented bit to see if
> the address is in canonical form. If a linear-memory reference is not in
> canonical form, the implementation should generate an exception. In most
> cases, a general-protection exception (#GP) is generated.
> -----Original Message-----
> From: Wu, Jiaxin <jiaxin...@intel.com>
> Sent: Wednesday, May 10, 2023 10:00 AM
> To: Gerd Hoffmann <kra...@redhat.com>; devel@edk2.groups.io
> Cc: Dong, Eric <eric.d...@intel.com>; Ni, Ray <ray...@intel.com>; Zeng, Star
> <star.z...@intel.com>; Kumar, Rahul R <rahul.r.ku...@intel.com>
> Subject: RE: [edk2-devel] [PATCH v1 1/3] UefiCpuPkg/SecCore: Migrate page
> table to permanent memory
>
> Hi Gerd,
>
> Could you share me which document introduce the sign-extended impact the
> line address width?
>
> Thanks,
> Jiaxin
>
> > -----Original Message-----
> > From: Gerd Hoffmann <kra...@redhat.com>
> > Sent: Tuesday, May 9, 2023 10:39 PM
> > To: devel@edk2.groups.io; Wu, Jiaxin <jiaxin...@intel.com>
> > Cc: Dong, Eric <eric.d...@intel.com>; Ni, Ray <ray...@intel.com>; Zeng, Star
> > <star.z...@intel.com>; Kumar, Rahul R <rahul.r.ku...@intel.com>
> > Subject: Re: [edk2-devel] [PATCH v1 1/3] UefiCpuPkg/SecCore: Migrate page
> > table to permanent memory
> >
> > Hi,
> >
> > > + if (PagingMode == Paging4Level1GB || PagingMode == Paging4Level) {
> > > + //
> > > + // The max lineaddress bits is 48 for 4 level page table.
> > > + //
> > > + VirPhyAddressSize.Bits.PhysicalAddressBits = MIN
> > (VirPhyAddressSize.Bits.PhysicalAddressBits, 48);
> > > + }
> >
> > virtual addresses in long mode are sign-extended. Which means you have
> > only 47 bits (or 56 bits with 5-level paging) for identity mappings.
> >
> > take care,
> > Gerd
-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#104475): https://edk2.groups.io/g/devel/message/104475
Mute This Topic: https://groups.io/mt/98780500/21656
Group Owner: devel+ow...@edk2.groups.io
Unsubscribe:
https://edk2.groups.io/g/devel/leave/9847357/21656/1706620634/xyzzy
[arch...@mail-archive.com]
-=-=-=-=-=-=-=-=-=-=-=-
