The changes look good to me. Please change the macro per comments to patch #1, then update this patch accordingly.
> -----Original Message----- > From: Liu, Zhiguang <zhiguang....@intel.com> > Sent: Friday, April 28, 2023 2:42 PM > To: devel@edk2.groups.io > Cc: Liu, Zhiguang <zhiguang....@intel.com>; Dong, Eric > <eric.d...@intel.com>; Ni, Ray <ray...@intel.com>; Kumar, Rahul R > <rahul.r.ku...@intel.com>; Gerd Hoffmann <kra...@redhat.com>; De, > Debkumar <debkumar...@intel.com>; West, Catharine > <catharine.w...@intel.com> > Subject: [PATCH v3 5/5] UefiCpuPkg/ResetVector: Support 5 level page table > in ResetVector > > Add a macro USE_5_LEVEL_PAGE_TABLE to determine whether to create > 5 level page table. > If macro USE_5_LEVEL_PAGE_TABLE is defined, PML5Table is created > at (4G-12K), while PML4Table is at (4G-16K). In runtime check, if > 5level paging is supported, use PML5Table, otherwise, use PML4Table. > If macro USE_5_LEVEL_PAGE_TABLE is not defined, to save space, 5level > paging is not created, and 4level paging is at (4G-12K) and be used. > > Cc: Eric Dong <eric.d...@intel.com> > Cc: Ray Ni <ray...@intel.com> > Cc: Rahul Kumar <rahul1.ku...@intel.com> > Cc: Gerd Hoffmann <kra...@redhat.com> > Cc: Debkumar De <debkumar...@intel.com> > Cc: Catharine West <catharine.w...@intel.com> > Signed-off-by: Zhiguang Liu <zhiguang....@intel.com> > --- > .../ResetVector/Vtf0/Ia32/Flat32ToFlat64.asm | 25 +++++++++++++++++-- > .../ResetVector/Vtf0/Ia32/PageTables64.asm | 24 ------------------ > UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb | 1 - > .../ResetVector/Vtf0/X64/PageTables.asm | 9 +++++++ > 4 files changed, 32 insertions(+), 27 deletions(-) > delete mode 100644 UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm > > diff --git a/UefiCpuPkg/ResetVector/Vtf0/Ia32/Flat32ToFlat64.asm > b/UefiCpuPkg/ResetVector/Vtf0/Ia32/Flat32ToFlat64.asm > index 6891397c2a..f119f941a5 100644 > --- a/UefiCpuPkg/ResetVector/Vtf0/Ia32/Flat32ToFlat64.asm > +++ b/UefiCpuPkg/ResetVector/Vtf0/Ia32/Flat32ToFlat64.asm > @@ -2,7 +2,7 @@ > ; @file > ; Transition from 32 bit flat protected mode into 64 bit flat protected mode > ; > -; Copyright (c) 2008 - 2018, Intel Corporation. All rights reserved.<BR> > +; Copyright (c) 2008 - 2023, Intel Corporation. All rights reserved.<BR> > ; SPDX-License-Identifier: BSD-2-Clause-Patent > ; > > ;------------------------------------------------------------------------------ > @@ -14,7 +14,28 @@ BITS 32 > ; > Transition32FlatTo64Flat: > > - OneTimeCall SetCr3ForPageTables64 > +%ifdef USE_5_LEVEL_PAGE_TABLE > + mov eax, 0 > + cpuid > + cmp eax, 07h ; check if basic CPUID leaf contains > leaf 07 > + jb NotSupport5LevelPaging ; 5level paging not support, > downgrade > to 4level paging > + mov eax, 07h ; check cpuid leaf 7, subleaf 0 > + mov ecx, 0 > + cpuid > + bt ecx, 16 ; [Bits 16] Supports 5-level paging > if 1. > + jnc NotSupport5LevelPaging ; 5level paging not support, > downgrade > to 4level paging > + mov eax, ADDR_OF(Pml5) > + mov cr3, eax > + mov eax, cr4 > + bts eax, 12 ; Set LA57=1. > + mov cr4, eax > + jmp SetCr3Done > +NotSupport5LevelPaging: > +%endif > + > + mov eax, ADDR_OF(Pml4) > + mov cr3, eax > +SetCr3Done: > > mov eax, cr4 > bts eax, 5 ; enable PAE > diff --git a/UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm > b/UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm > deleted file mode 100644 > index f188da20ba..0000000000 > --- a/UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm > +++ /dev/null > @@ -1,24 +0,0 @@ > -;------------------------------------------------------------------------------ > -; @file > -; Sets the CR3 register for 64-bit paging > -; > -; Copyright (c) 2008 - 2023, Intel Corporation. All rights reserved.<BR> > -; SPDX-License-Identifier: BSD-2-Clause-Patent > -; > -;------------------------------------------------------------------------------ > - > -BITS 32 > - > -; > -; Modified: EAX > -; > -SetCr3ForPageTables64: > - > - ; > - ; These pages are built into the ROM image in X64/PageTables.asm > - ; > - mov eax, ADDR_OF(Pml4) > - mov cr3, eax > - > - OneTimeCallRet SetCr3ForPageTables64 > - > diff --git a/UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb > b/UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb > index 136361e62c..5a6563bd34 100644 > --- a/UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb > +++ b/UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb > @@ -54,7 +54,6 @@ > > %ifdef ARCH_X64 > %include "Ia32/Flat32ToFlat64.asm" > -%include "Ia32/PageTables64.asm" > %endif > > %include "Ia16/Real16ToFlat32.asm" > diff --git a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables.asm > b/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables.asm > index 4ff68cddef..5aa229eb14 100644 > --- a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables.asm > +++ b/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables.asm > @@ -80,4 +80,13 @@ Pml4: > ; > DQ PG_NLE(Pdp) > TIMES 0x1000 - ($ - Pml4) DB 0 > + > +%ifdef USE_5_LEVEL_PAGE_TABLE > +Pml5: > + ; > + ; Pml5 table (only first entry is present, pointing to Pml4) > + ; > + DQ PG_NLE(Pml4) > + TIMES 0x1000 - ($ - Pml5) DB 0 > +%endif > EndOfPageTables: > -- > 2.31.1.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. 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