The changes look good to me. Please change the macro per comments to patch #1, then update this patch accordingly.
> -----Original Message----- > From: Liu, Zhiguang <zhiguang....@intel.com> > Sent: Friday, April 28, 2023 2:42 PM > To: devel@edk2.groups.io > Cc: Liu, Zhiguang <zhiguang....@intel.com>; Dong, Eric > <eric.d...@intel.com>; Ni, Ray <ray...@intel.com>; Kumar, Rahul R > <rahul.r.ku...@intel.com>; Gerd Hoffmann <kra...@redhat.com>; De, > Debkumar <debkumar...@intel.com>; West, Catharine > <catharine.w...@intel.com> > Subject: [PATCH v3 4/5] UefiCpuPkg/ResetVector: Modify Page Table in > ResetVector > > In ResetVector, if create page table, its highest address is fixed > because after page table, code layout is fixed(4K for normal code, > and another 4K only contains reset vector code). > Today's implementation organizes the page table as following if 1G > page table is used: > 4G-16K: PML4 page (PML4[0] points to 4G-12K) > 4G-12K: PDP page > CR3 is set to 4G-16K > When 2M page table is used, the layout is as following: > 4G-32K: PML4 page (PML4[0] points to 4G-28K) > 4G-28K: PDP page (PDP entries point to PD pages) > 4G-24K: PD page mapping 0-1G > 4G-20K: PD page mapping 1-2G > 4G-16K: PD page mapping 2-3G > 4G-12K: PD page mapping 3-4G > CR3 is set to 4G-32K > CR3 doesn't point to a fixed location which is a bit hard to debug at > runtime. > > The new page table layout will always put PML4 in highest address > When 1G page table is used, the layout is as following: > 4G-16K: PDP page > 4G-12K: PML4 page (PML4[0] points to 4G-16K) > When 2M page table is used, the layout is as following: > 4G-32K: PD page mapping 0-1G > 4G-28K: PD page mapping 1-2G > 4G-24K: PD page mapping 2-3G > 4G-20K: PD page mapping 3-4G > 4G-16K: PDP page (PDP entries point to PD pages) > 4G-12K: PML4 page (PML4[0] points to 4G-16K) > CR3 is always set to 4G-12K > So, this patch can improve biodegradability by make sure the init > CR3 pointing to a fixed address(4G-12K). > > Cc: Eric Dong <eric.d...@intel.com> > Cc: Ray Ni <ray...@intel.com> > Cc: Rahul Kumar <rahul1.ku...@intel.com> > Cc: Gerd Hoffmann <kra...@redhat.com> > Cc: Debkumar De <debkumar...@intel.com> > Cc: Catharine West <catharine.w...@intel.com> > Signed-off-by: Zhiguang Liu <zhiguang....@intel.com> > --- > .../ResetVector/Vtf0/X64/PageTables.asm | 32 +++++++++---------- > 1 file changed, 16 insertions(+), 16 deletions(-) > > diff --git a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables.asm > b/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables.asm > index 469fed0006..4ff68cddef 100644 > --- a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables.asm > +++ b/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables.asm > @@ -41,13 +41,6 @@ BITS 64 > > ALIGN 16 > > -Pml4: > - ; > - ; PML4 (1 * 512GB entry) > - ; > - DQ PG_NLE(Pdp) > - TIMES 0x1000 - ($ - Pml4) DB 0 > - > %ifdef PAGE_TABLE_1G > Pdp: > ; > @@ -59,6 +52,16 @@ Pdp: > %assign i i+1 > %endrep > %else > +Pd: > + ; > + ; Page-Directory (2048 * 2MB entries => 4GB) > + ; Four pages below, each is pointed by one entry in Pdp. > + ; > + %assign i 0 > + %rep 0x800 > + DQ PTE_2MB(i) > + %assign i i+1 > + %endrep > Pdp: > ; > ; Page-directory pointer table (4 * 1GB entries => 4GB) > @@ -69,15 +72,12 @@ Pdp: > DQ PG_NLE(Pd + 0x3000) > TIMES 0x1000 - ($ - Pdp) DB 0 > > -Pd: > +%endif > + > +Pml4: > ; > - ; Page-Directory (2048 * 2MB entries => 4GB) > - ; Four pages below, each is pointed by one entry in Pdp. > + ; PML4 (1 * 512GB entry) > ; > - %assign i 0 > - %rep 0x800 > - DQ PTE_2MB(i) > - %assign i i+1 > - %endrep > -%endif > + DQ PG_NLE(Pdp) > + TIMES 0x1000 - ($ - Pml4) DB 0 > EndOfPageTables: > -- > 2.31.1.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#103771): https://edk2.groups.io/g/devel/message/103771 Mute This Topic: https://groups.io/mt/98553403/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/leave/9847357/21656/1706620634/xyzzy [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
