> > There are no PEI module changes in this patch series. > > So where does the HOB come from? >
Who use, who produce. Here, just provide the interface capability. > And what are the reasons for setting SMBASE in a PEI module instead > of PiSmmCpuDxeSmm? > Do the smbase relocated ahead of SMM cpu driver can bring the benefit as I explain in the patch 2: PiSmmCpuDxeSmm will retrieve the SMBASE addresses from SMM Base Hob and installs the SMI handler at [SMBASE+8000h] for each processor instead of relocating SMM Base addresses from SMRAM again. With SMM Base Hob, PiSmmCpuDxeSmm does not need the RSM instruction to reload the SMBASE register with the new allocated SMBASE each time when it exits SMM. SMBASE Register for each processors have already been programmed and all SMBASE address have recorded in SMM Base Hob. So the same default SMBASE Address (0x30000) will not be used, thus the CPUs over-writing each other's SMM Save State Area will not happen. This way makes the first SMI init can be executed in parallel and save boot time on multi-core system. > take care, > Gerd -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#98478): https://edk2.groups.io/g/devel/message/98478 Mute This Topic: https://groups.io/mt/96241699/21656 Group Owner: [email protected] Unsubscribe: https://edk2.groups.io/g/devel/unsub [[email protected]] -=-=-=-=-=-=-=-=-=-=-=-
