Thanks for the feedback Michael. This has been addressed in the new V2 series.
-----Original Message-----
From: Michael Kubacki <mikub...@linux.microsoft.com>
Sent: Monday, June 6, 2022 3:56 PM
To: devel@edk2.groups.io; Desimone, Nathaniel L <nathaniel.l.desim...@intel.com>
Cc: Chiu, Chasel <chasel.c...@intel.com>; Sinha, Ankit <ankit.si...@intel.com>;
Kubacki, Michael <michael.kuba...@microsoft.com>; Benjamin Doron
<benjamin.doro...@gmail.com>; Soller, Jeremy <jer...@system76.com>
Subject: Re: [edk2-devel] [edk2-platforms] [PATCH V1 1/4] KabylakeOpenBoardPkg:
Indicate width of CLK duty cycle in FADT
It seems the FSP changes should at least be in a separate commit even if a part
of this overall series.
Regards,
Michael
On 6/6/2022 6:50 PM, Nate DeSimone wrote:
> Set the location of the DUTY_CYCLE field in the P_CNT register and
> indicate the width of the clock duty cycle to OS power management
>
> Merged missing PCD settings into GalagoPro3
>
> Cc: Chasel Chiu <chasel.c...@intel.com>
> Cc: Ankit Sinha <ankit.si...@intel.com>
> Cc: Michael Kubacki <michael.kuba...@microsoft.com>
> Cc: Benjamin Doron <benjamin.doro...@gmail.com>
> Cc: Jeremy Soller <jer...@system76.com>
> Signed-off-by: Nate DeSimone <nathaniel.l.desim...@intel.com>
> ---
> .../AspireVn7Dash572G/OpenBoardPkgPcd.dsc | 9 +++-
> .../GalagoPro3/OpenBoardPkgPcd.dsc | 52 +++++++++++++++++--
> .../KabylakeRvp3/OpenBoardPkgPcd.dsc | 11 +++-
> 3 files changed, 65 insertions(+), 7 deletions(-)
>
> diff --git
> a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkgPc
> d.dsc
> b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkgPc
> d.dsc
> index 21ee86403d..02080aa864 100644
> ---
> a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkgPc
> d.dsc
> +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardP
> +++ kgPcd.dsc
> @@ -1,7 +1,7 @@
> ## @file
> # PCD configuration build description file for the Aspire VN7-572G board.
> #
> -# Copyright (c) 2017 - 2020, Intel Corporation. All rights
> reserved.<BR>
> +# Copyright (c) 2017 - 2022, Intel Corporation. All rights
> +reserved.<BR>
> #
> # SPDX-License-Identifier: BSD-2-Clause-Patent
> #
> @@ -346,6 +346,13 @@
> gSiPkgTokenSpaceGuid.PcdHstiIhvFeature1|0xF2 # FIXME: Boot Guard and
> BIOS Guard not present, measured boot enforcement checking code not present
> gSiPkgTokenSpaceGuid.PcdHstiIhvFeature2|0x07
>
> + #
> + # Set the location of the DUTY_CYCLE field in the P_CNT register #
> + and indicate the width of the clock duty cycle to OS power
> + management #
> + gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyOffset|0x1
> + gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyWidth|0x3
> +
> ######################################
> # Platform Configuration
> ######################################
> diff --git
> a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.dsc
> b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.dsc
> index 44dacdf082..26e2c16aae 100644
> ---
> a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.dsc
> +++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.d
> +++ sc
> @@ -1,7 +1,7 @@
> ## @file
> # PCD configuration build description file for the GalagoPro3 board.
> #
> -# Copyright (c) 2019 - 2020, Intel Corporation. All rights
> reserved.<BR>
> +# Copyright (c) 2019 - 2022, Intel Corporation. All rights
> +reserved.<BR>
> #
> # SPDX-License-Identifier: BSD-2-Clause-Patent
> #
> @@ -40,6 +40,26 @@
> #
> gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode|TRUE
>
> + #
> + # FALSE: The PEI Main included in FvPreMemory is used to dispatch all PEIMs
> + # (both inside FSP and outside FSP).
> + # Pros:
> + # * PEI Main is re-built from source and is always the latest
> version
> + # * Platform code can link any desired LibraryClass to PEI Main
> + # (Ex: Custom DebugLib instance, SerialPortLib, etc.)
> + # Cons:
> + # * The PEI Main being used to execute FSP PEIMs is not the PEI
> Main
> + # that the FSP PEIMs were tested with, adding risk of breakage.
> + # * Two copies of PEI Main will exist in the final binary,
> + # #1 in FSP-M, #2 in FvPreMemory. The copy in FSP-M is never
> + # executed, wasting space.
> + #
> + # <b>TRUE</b>: The PEI Main included in FSP is used to dispatch all PEIMs
> + # (both inside FSP and outside FSP). PEI Main will not be included
> in
> + # FvPreMemory. This is the default and is the recommended choice.
> + #
> + gMinPlatformPkgTokenSpaceGuid.PcdFspDispatchModeUseFspPeiMain|TRUE
> +
> #
> # FSP Base address PCD will be updated in FDF basing on flash map.
> #
> @@ -52,6 +72,7 @@
> gSiPkgTokenSpaceGuid.PcdTemporaryRamSize|0x00040000
> gSiPkgTokenSpaceGuid.PcdTsegSize|0x1000000
>
> +!if gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection == 1
> #
> # FSP API mode does not share stack with the boot loader,
> # so FSP needs more temporary memory for FSP heap + stack size.
> @@ -63,6 +84,24 @@
> # since the stacks are separate.
> #
> gSiPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize|0x20000
> +!else
> + #
> + # In FSP Dispatch mode boot loader stack size must be large
> + # enough for executing both boot loader and FSP.
> + #
> + gSiPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize|0x40000
> +!endif
> +
> +!if (gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode == FALSE) ||
> +(gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection == 1)
> +
> +gSiPkgTokenSpaceGuid.PcdSiPciExpressBaseAddress|gEfiMdePkgTokenSpaceG
> +uid.PcdPciExpressBaseAddress
> +
> +gSiPkgTokenSpaceGuid.PcdSiPciExpressRegionLength|gMinPlatformPkgToken
> +SpaceGuid.PcdPciExpressRegionLength
> +!else
> + #
> + # FSP Dispatch mode requires more platform memory as boot loader
> +and FSP sharing the same
> + # platform memory.
> + #
> + gSiPkgTokenSpaceGuid.PcdPeiMinMemorySize|0x5500000
> +!endif
>
> [PcdsFeatureFlag.common]
> ######################################
> @@ -222,7 +261,7 @@
> gUefiCpuPkgTokenSpaceGuid.PcdCpuApInitTimeOutInMicroSeconds|1000
> gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmApSyncTimeout|10000
> gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackSize|0x20000
> -
> +!if (gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode == FALSE) ||
> +(gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection == 1)
> #
> # In non-FSP build (EDK2 build) or FSP API mode below PCD are FixedAtBuild
> # (They will be DynamicEx in FSP Dispatch mode) @@ -242,6 +281,7
> @@
> # 3: Place AP in the Run-Loop state.
> # @Prompt The AP wait loop state.
> gUefiCpuPkgTokenSpaceGuid.PcdCpuApLoopMode|2
> +!endif
>
> ######################################
> # Silicon Configuration
> @@ -251,8 +291,12 @@
> gSiPkgTokenSpaceGuid.PcdHstiIhvFeature1|0xF2
> gSiPkgTokenSpaceGuid.PcdHstiIhvFeature2|0x07
>
> -
> gSiPkgTokenSpaceGuid.PcdSiPciExpressBaseAddress|gEfiMdePkgTokenSpaceGu
> id.PcdPciExpressBaseAddress
> -
> gSiPkgTokenSpaceGuid.PcdSiPciExpressRegionLength|gMinPlatformPkgTokenS
> paceGuid.PcdPciExpressRegionLength
> + #
> + # Set the location of the DUTY_CYCLE field in the P_CNT register #
> + and indicate the width of the clock duty cycle to OS power
> + management #
> + gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyOffset|0x1
> + gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyWidth|0x3
>
> ######################################
> # Platform Configuration
> diff --git
> a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc
> b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc
> index 725596cbf7..ccf757e202 100644
> ---
> a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc
> +++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd
> +++ .dsc
> @@ -1,7 +1,7 @@
> ## @file
> # PCD configuration build description file for the KabylakeRvp3 board.
> #
> -# Copyright (c) 2017 - 2020, Intel Corporation. All rights
> reserved.<BR>
> +# Copyright (c) 2017 - 2022, Intel Corporation. All rights
> +reserved.<BR>
> #
> # SPDX-License-Identifier: BSD-2-Clause-Patent
> #
> @@ -78,6 +78,7 @@
> # so FSP needs more temporary memory for FSP heap + stack size.
> #
> gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize|0x26000
> +
> #
> # FSP API mode does not need to enlarge the boot loader stack size
> # since the stacks are separate.
> @@ -290,6 +291,13 @@
> gSiPkgTokenSpaceGuid.PcdHstiIhvFeature1|0xF2
> gSiPkgTokenSpaceGuid.PcdHstiIhvFeature2|0x07
>
> + #
> + # Set the location of the DUTY_CYCLE field in the P_CNT register #
> + and indicate the width of the clock duty cycle to OS power
> + management #
> + gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyOffset|0x1
> + gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyWidth|0x3
> +
> ######################################
> # Platform Configuration
> ######################################
> @@ -346,7 +354,6 @@
> gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x0F,
> 0x07, 0x1F, 0x1F, 0x0F, 0x0F, 0x07, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> 0x00}
> !endif
>
> -
> ######################################
> # Board Configuration
> ######################################
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