On Mon, Feb 28, 2022 at 03:20:55PM +0800, Min Xu wrote: > RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3429 > > There are below major changes in this commit. > > 1. SecEntry.nasm > In TDX BSP and APs goes to the same entry point in SecEntry.nasm. > > BSP initialize the temporary stack and then jumps to SecMain, just as > legacy Ovmf does. > > APs spin in a modified mailbox loop using initial mailbox structure. > Its structure defition is in OvmfPkg/Include/IndustryStandard/IntelTdx.h. > APs wait for command to see if the command is for me. If so execute the > command. > > 2. Sec/SecMain.c > When host VMM create the Td guest, the system memory informations are > stored in TdHob, which is a memory region described in Tdx metadata. > The system memory region in TdHob should be accepted before it can be > accessed. So the major task of this patch is to process the TdHobList > to accept the memory. After that TDVF follow the standard OVMF flow > and jump to PEI phase. > > PcdUse1GPageTable is set to FALSE by default in OvmfPkgX64.dsc. It gives > no chance for Intel TDX to support 1G page table. To support 1G page > table this PCD is set to TRUE in OvmfPkgX64.dsc. > > TDX_GUEST_SUPPORTED is defined in OvmfPkgX64.dsc. This macro wraps the > Tdx specific code. > > TDX only works on X64, so the code is only valid in X64 arch. > > Cc: Ard Biesheuvel <ardb+tianoc...@kernel.org> > Cc: Jordan Justen <jordan.l.jus...@intel.com> > Cc: Brijesh Singh <brijesh.si...@amd.com> > Cc: Erdem Aktas <erdemak...@google.com> > Cc: James Bottomley <j...@linux.ibm.com> > Cc: Jiewen Yao <jiewen....@intel.com> > Cc: Tom Lendacky <thomas.lenda...@amd.com> > Cc: Gerd Hoffmann <kra...@redhat.com> > Signed-off-by: Min Xu <min.m...@intel.com>
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