OnFebruary 23, 2022 6:14 PM, Gerd Hoffmann wrote:
> > - Pml4Entries = 1 << (mPhysMemAddressWidth - 39);
> > + if (TdIsEnabled ()) {
> > + Pml4Entries = 0x200;
> > + } else {
> > + Pml4Entries = 1 << (mPhysMemAddressWidth - 39);
> > + }
>
> With the PlatformAddressWidthInitialization() update in patch #33 it should
> not be needed to special-case TDX here. You might need a check for 5-level
> paging support (mPhysMemAddressWidth > 48) though, or just cap
> Pml4Entries at 512 entries.
>
As we agree in current stage 5-level paging is not supported, I will cap
Pml4Entries at 512 entries when mPhysMemAddressWidth > 48.
Thanks
Min
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