On Sat, 29 Jan 2022 15:52:02 +0000,
Ard Biesheuvel <a...@kernel.org> wrote:
>
> (+ Marc)
>
> On Fri, 28 Jan 2022 at 16:41, <pierre.gond...@arm.com> wrote:
> >
> > From: Pierre Gondois <pierre.gond...@arm.com>
> >
> > In ACPI 6.4, s6.2.13, _PRT objects describing PCI legacy interrupts
> > can be defined following 2 models.
> > In the first model, a _SRS object must be described to modify the PCI
> > interrupt. The _CRS and _PRS object allows to describe the PCI
> > interrupt (level/edge triggered, active high/low).
> > In the second model, the PCI interrupt cannot be described with a
> > similar granularity. PCI interrupts are by default level triggered,
> > active low.
> >
> > GicV2 SPI interrupts are level or edge triggered, active high. To
> > correctly describe PCI interrupts, the first model is used, even though
> > Arm Base Boot Requirements v1.0 requires to use the second mode.
> >
>
> There are two different issues here:
>
> - using separate 'interrupt link' device objects with an Interrupt()
> resource rather than a simple GSIV number
> - whether _PRS and _SRS need to be implemented on those link objects.
>
> The latter is simply not true - _PRS and _SRS are optional, and
> pointless if there is only a single possible value, so there is really
> no need to add them here.
>
> As for the choice between the link object or the GSIV number: I don't
> think INTx interrupts on ARM systems are actually level low, and the
> GSIV option is widely used, also in platforms that exist in
> edk2-platforms, without any reported issues.
>
> I've cc'ed Marc, perhaps he can shed some light on this, but I'd
> prefer to stick to the GSIV approach if we can, as it is much simpler.
I don't immediately see the point either. Yes, the GIC only supports
level-high interrupts. However, all the PCIe implementations connected
to it are inverting the level. If they don't, that's even simpler (the
HW is broken).
Is this to address an apparent disconnect with the spec?
[...]
> > - The _PRS and _SRS are not supported, cf Arm Base Boot Requirements v1.0:
> > + Warning: The Arm Base Boot Requirements v1.0 states the following:
> > "The _PRS (Possible Resource Settings) and _SRS (Set Resource Settings)
> > are not supported."
> > + However, the first model to describe PCI legacy interrupts is used (cf.
> > ACPI
> > + 6.4 s6.2.13) as PCI defaults (Level Triggered, Active Low) are not
> > compatible
> > + with GICv2 (must be Active High).
nit: GICv3 has the exact same behaviour. Why is v2 singled out?
Thanks,
M.
--
Without deviation from the norm, progress is not possible.
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