From: Anurag Koul <anurag.k...@arm.com>
This commit adds:
- SSDT, MCFG table for PCIe and CCIX RC nodes
- IORT nodes bindings for PCIe/CCIX and the associated ITSs and SMMUs
in the Configuration Manager.
Signed-off-by: Anurag Koul <anurag.k...@arm.com>
Signed-off-by: Chandni Cherukuri <chandni.cheruk...@arm.com>
---
Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxeSoc.inf
| 35 ++
Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerSoc.h
| 26 +-
Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerSoc.c
| 596 +++++++++++++++++++-
Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/AslTables/SsdtPciSoc.asl
| 223 ++++++++
4 files changed, 877 insertions(+), 3 deletions(-)
diff --git
a/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxeSoc.inf
b/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxeSoc.inf
index 6f9199a6fda2..fb6f72684148 100644
---
a/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxeSoc.inf
+++
b/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxeSoc.inf
@@ -22,6 +22,7 @@
[Sources]
AslTables/DsdtSoc.asl
+ AslTables/SsdtPciSoc.asl
ConfigurationManager.c
ConfigurationManager.h
ConfigurationManagerSoc.c
@@ -43,6 +44,40 @@
gEdkiiConfigurationManagerProtocolGuid
[FixedPcd]
+ gArmMorelloTokenSpaceGuid.PcdPciBusCount
+ gArmMorelloTokenSpaceGuid.PcdPciBusMax
+ gArmMorelloTokenSpaceGuid.PcdPciBusMin
+ gArmMorelloTokenSpaceGuid.PcdPciExpressBaseAddress
+ gArmMorelloTokenSpaceGuid.PcdPciIoBase
+ gArmMorelloTokenSpaceGuid.PcdPciIoMaxBase
+ gArmMorelloTokenSpaceGuid.PcdPciIoSize
+ gArmMorelloTokenSpaceGuid.PcdPciIoTranslation
+ gArmMorelloTokenSpaceGuid.PcdPciMmio32Base
+ gArmMorelloTokenSpaceGuid.PcdPciMmio32MaxBase
+ gArmMorelloTokenSpaceGuid.PcdPciMmio32Size
+ gArmMorelloTokenSpaceGuid.PcdPciMmio32Translation
+ gArmMorelloTokenSpaceGuid.PcdPciMmio64Base
+ gArmMorelloTokenSpaceGuid.PcdPciMmio64MaxBase
+ gArmMorelloTokenSpaceGuid.PcdPciMmio64Size
+ gArmMorelloTokenSpaceGuid.PcdPciMmio64Translation
+
+ gArmMorelloTokenSpaceGuid.PcdCcixBusCount
+ gArmMorelloTokenSpaceGuid.PcdCcixBusMax
+ gArmMorelloTokenSpaceGuid.PcdCcixBusMin
+ gArmMorelloTokenSpaceGuid.PcdCcixExpressBaseAddress
+ gArmMorelloTokenSpaceGuid.PcdCcixIoBase
+ gArmMorelloTokenSpaceGuid.PcdCcixIoMaxBase
+ gArmMorelloTokenSpaceGuid.PcdCcixIoSize
+ gArmMorelloTokenSpaceGuid.PcdCcixIoTranslation
+ gArmMorelloTokenSpaceGuid.PcdCcixMmio32Base
+ gArmMorelloTokenSpaceGuid.PcdCcixMmio32MaxBase
+ gArmMorelloTokenSpaceGuid.PcdCcixMmio32Size
+ gArmMorelloTokenSpaceGuid.PcdCcixMmio32Translation
+ gArmMorelloTokenSpaceGuid.PcdCcixMmio64Base
+ gArmMorelloTokenSpaceGuid.PcdCcixMmio64MaxBase
+ gArmMorelloTokenSpaceGuid.PcdCcixMmio64Size
+ gArmMorelloTokenSpaceGuid.PcdCcixMmio64Translation
+
## PL011 Serial Debug UART
gArmPlatformTokenSpaceGuid.PcdSerialDbgRegisterBase
gArmPlatformTokenSpaceGuid.PcdSerialDbgUartBaudRate
diff --git
a/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerSoc.h
b/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerSoc.h
index 8a521b83c8dc..fc0bbabdd1aa 100644
---
a/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerSoc.h
+++
b/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerSoc.h
@@ -16,7 +16,7 @@
/** The number of ACPI tables to install
*/
-#define PLAT_ACPI_TABLE_COUNT 7
+#define PLAT_ACPI_TABLE_COUNT 10
/** A helper macro for mapping a reference token
*/
@@ -29,12 +29,34 @@
containing the AML bytecode array.
*/
extern CHAR8 dsdtsoc_aml_code[];
+extern CHAR8 ssdtpcisoc_aml_code[];
/** A structure describing the SoC Platform specific information
*/
typedef struct SocPlatformRepositoryInfo {
/// List of ACPI tables
- CM_STD_OBJ_ACPI_TABLE_INFO CmAcpiTableList[PLAT_ACPI_TABLE_COUNT];
+ CM_STD_OBJ_ACPI_TABLE_INFO CmAcpiTableList[PLAT_ACPI_TABLE_COUNT];
+
+ /// GIC ITS information
+ CM_ARM_GIC_ITS_INFO GicItsInfo[4];
+
+ /// ITS Group node
+ CM_ARM_ITS_GROUP_NODE ItsGroupInfo[4];
+
+ /// ITS Identifier array
+ CM_ARM_ITS_IDENTIFIER ItsIdentifierArray[4];
+
+ /// SMMUv3 node
+ CM_ARM_SMMUV3_NODE SmmuV3Info[2];
+
+ /// PCI Root complex node
+ CM_ARM_ROOT_COMPLEX_NODE RootComplexInfo[2];
+
+ /// Array of DeviceID mapping
+ CM_ARM_ID_MAPPING DeviceIdMapping[3][2];
+
+ /// PCI configuration space information
+ CM_ARM_PCI_CONFIG_SPACE_INFO PciConfigInfo[2];
} EDKII_SOC_PLATFORM_REPOSITORY_INFO;
/** A structure describing the platform configuration
diff --git
a/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerSoc.c
b/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerSoc.c
index 7ca8ae212a61..f4ad6d934f0c 100644
---
a/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerSoc.c
+++
b/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerSoc.c
@@ -73,6 +73,341 @@ EDKII_SOC_PLATFORM_REPOSITORY_INFO
MorelloSocRepositoryInfo = {
CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdPptt),
NULL
},
+ // IORT Table
+ {
+ EFI_ACPI_6_3_IO_REMAPPING_TABLE_SIGNATURE,
+ EFI_ACPI_IO_REMAPPING_TABLE_REVISION,
+ CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdIort),
+ NULL
+ },
+ // PCI MCFG Table
+ {
+
EFI_ACPI_6_3_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE,
+ EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_TABLE_REVISION,
+ CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdMcfg),
+ NULL,
+ },
+ // SSDT table describing the PCI root complex
+ {
+ EFI_ACPI_6_3_SECONDARY_SYSTEM_DESCRIPTION_TABLE_SIGNATURE,
+ 0, // Unused
+ CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdSsdt),
+ (EFI_ACPI_DESCRIPTION_HEADER *)ssdtpcisoc_aml_code
+ },
+ },
+
+ // GIC ITS
+ {
+ // GIC ITS - PCIe TCU
+ {
+ // The GIC ITS ID.
+ 0,
+ // The physical address for the Interrupt Translation Service
+ 0x30060000,
+ // Proximity Domain
+ 0
+ },
+ // GIC ITS - PCIe RC
+ {
+ // The GIC ITS ID.
+ 1,
+ // The physical address for the Interrupt Translation Service
+ 0x300A0000,
+ // Proximity Domain
+ 0
+ },
+ // GIC ITS - CCIX TCU
+ {
+ // The GIC ITS ID.
+ 2,
+ // The physical address for the Interrupt Translation Service
+ 0x30040000,
+ // Proximity Domain
+ 0
+ },
+ // GIC ITS - CCIX RC
+ {
+ // The GIC ITS ID.
+ 3,
+ // The physical address for the Interrupt Translation Service
+ 0x30080000,
+ // Proximity Domain
+ 0
+ },
+ },
+
+ // ITS group node
+ {
+ {
+ // Reference token for this Iort node
+ REFERENCE_TOKEN_SOC (ItsGroupInfo[0]),
+ // The number of ITS identifiers in the ITS node.
+ 1,
+ // Reference token for the ITS identifier array
+ REFERENCE_TOKEN_SOC (ItsIdentifierArray[0])
+ },
+ {
+ // Reference token for this Iort node
+ REFERENCE_TOKEN_SOC (ItsGroupInfo[1]),
+ // The number of ITS identifiers in the ITS node.
+ 1,
+ // Reference token for the ITS identifier array
+ REFERENCE_TOKEN_SOC (ItsIdentifierArray[1])
+ },
+ {
+ // Reference token for this Iort node
+ REFERENCE_TOKEN_SOC (ItsGroupInfo[2]),
+ // The number of ITS identifiers in the ITS node.
+ 1,
+ // Reference token for the ITS identifier array
+ REFERENCE_TOKEN_SOC (ItsIdentifierArray[2])
+ },
+ {
+ // Reference token for this Iort node
+ REFERENCE_TOKEN_SOC (ItsGroupInfo[3]),
+ // The number of ITS identifiers in the ITS node.
+ 1,
+ // Reference token for the ITS identifier array
+ REFERENCE_TOKEN_SOC (ItsIdentifierArray[3])
+ },
+ },
+
+ // ITS identifier array
+ {
+ {
+ // The ITS Identifier
+ 0
+ },
+ {
+ // The ITS Identifier
+ 1
+ },
+ {
+ // The ITS Identifier
+ 2
+ },
+ {
+ // The ITS Identifier
+ 3
+ },
+ },
+
+ // SMMUv3 Node
+ {
+ {
+ // Reference token for this Iort node
+ REFERENCE_TOKEN_SOC (SmmuV3Info[0]),
+ // Number of ID mappings
+ 2,
+ // Reference token for the ID mapping array
+ REFERENCE_TOKEN_SOC (DeviceIdMapping[0][0]),
+ // SMMU Base Address
+ 0x4F400000,
+ // SMMU flags
+ EFI_ACPI_IORT_SMMUv3_FLAG_COHAC_OVERRIDE,
+ // VATOS address
+ 0,
+ // Model
+ EFI_ACPI_IORT_SMMUv3_MODEL_GENERIC,
+ // GSIV of the Event interrupt if SPI based
+ 267,
+ // PRI Interrupt if SPI based
+ 72,
+ // GERR interrupt if GSIV based
+ 269,
+ // Sync interrupt if GSIV based
+ 268,
+ // Proximity domain flag, ignored in this case
+ 0,
+ // Index into the array of ID mapping
+ 1
+ },
+ {
+ // Reference token for this Iort node
+ REFERENCE_TOKEN_SOC (SmmuV3Info[1]),
+ // Number of ID mappings
+ 2,
+ // Reference token for the ID mapping array
+ REFERENCE_TOKEN_SOC (DeviceIdMapping[2][0]),
+ // SMMU Base Address
+ 0x4F000000,
+ // SMMU flags
+ EFI_ACPI_IORT_SMMUv3_FLAG_COHAC_OVERRIDE,
+ // VATOS address
+ 0,
+ // Model
+ EFI_ACPI_IORT_SMMUv3_MODEL_GENERIC,
+ // GSIV of the Event interrupt if SPI based
+ 260,
+ // PRI Interrupt if SPI based
+ 73,
+ // GERR interrupt if GSIV based
+ 262,
+ // Sync interrupt if GSIV based
+ 261,
+ // Proximity domain flag, ignored in this case
+ 0,
+ // Index into the array of ID mapping
+ 1
+ },
+ },
+
+ // Root Complex node info
+ {
+ {
+ // Reference token for this Iort node
+ REFERENCE_TOKEN_SOC (RootComplexInfo[0]),
+ // Number of ID mappings
+ 1,
+ // Reference token for the ID mapping array
+ REFERENCE_TOKEN_SOC (DeviceIdMapping[1][0]),
+
+ // Memory access properties : Cache coherent attributes
+ EFI_ACPI_IORT_MEM_ACCESS_PROP_CCA,
+ // Memory access properties : Allocation hints
+ 0,
+ // Memory access properties : Memory access flags
+ 0,
+ // ATS attributes
+ 3,
+ // PCI segment number
+ 0,
+ // Memory address size limit
+ 42
+ },
+ {
+ // Reference token for this Iort node
+ REFERENCE_TOKEN_SOC (RootComplexInfo[1]),
+ // Number of ID mappings
+ 1,
+ // Reference token for the ID mapping array
+ REFERENCE_TOKEN_SOC (DeviceIdMapping[1][1]),
+
+ // Memory access properties : Cache coherent attributes
+ EFI_ACPI_IORT_MEM_ACCESS_PROP_CCA,
+ // Memory access properties : Allocation hints
+ 0,
+ // Memory access properties : Memory access flags
+ 0,
+ // ATS attributes
+ 3,
+ // PCI segment number
+ 1,
+ // Memory address size limit
+ 42
+ },
+ },
+
+ // Array of Device ID mappings
+ {
+ // DeviceIdMapping[0][0] - [0][1]
+ {
+ /* Mapping SMMUv3 -> ITS Group
+ */
+
+ // SMMUv3 device ID mapping
+ {
+ // Input base
+ 0x0,
+ // Number of input IDs
+ 0x0000FFFF,
+ // Output Base
+ 0x0,
+ // Output reference
+ REFERENCE_TOKEN_SOC (ItsGroupInfo[1]),
+ // Flags
+ 0
+ },
+ // SMMUv3 device ID mapping
+ {
+ // Input base
+ 0x0,
+ // Number of input IDs
+ 0x00000001,
+ // Output Base
+ 0x0,
+ // Output reference token for the IORT node
+ REFERENCE_TOKEN_SOC (ItsGroupInfo[0]),
+ // Flags
+ EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE
+ }
+ },
+ // Device ID mapping [1][0] - [1][1]
+ {
+ // Mapping for RootComplex -> SMMUv3
+ {
+ // Input base
+ 0x0,
+ // Number of input IDs
+ 0x0000FFFF,
+ // Output Base
+ 0x0,
+ // Output reference
+ REFERENCE_TOKEN_SOC (SmmuV3Info[0]),
+ // Flags
+ 0
+ },
+ {
+ // Input base
+ 0x0,
+ // Number of input IDs
+ 0x0000FFFF,
+ // Output Base
+ 0x0,
+ // Output reference
+ REFERENCE_TOKEN_SOC (SmmuV3Info[1]),
+ // Flags
+ 0
+ },
+ },
+ // DeviceIdMapping[2][0] - [2][1]
+ {
+ /* Mapping SMMUv3 -> ITS Group
+ */
+ // SMMUv3 device ID mapping
+ {
+ // Input base
+ 0x0,
+ // Number of input IDs
+ 0x0000FFFF,
+ // Output Base
+ 0x0,
+ // Output reference
+ REFERENCE_TOKEN_SOC (ItsGroupInfo[3]),
+ // Flags
+ 0
+ },
+ // SMMUv3 device ID mapping
+ {
+ // Input base
+ 0x0,
+ // Number of input IDs
+ 0x00000001,
+ // Output Base
+ 0x0,
+ // Output reference token for the IORT node
+ REFERENCE_TOKEN_SOC (ItsGroupInfo[2]),
+ // Flags
+ EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE
+ }
+ },
+ },
+ // PCI Configuration Space Info
+ {
+ // PCIe ECAM
+ {
+ FixedPcdGet64 (PcdPciExpressBaseAddress), // Base Address
+ 0x0, // Segment Group Number
+ FixedPcdGet32 (PcdPciBusMin), // Start Bus Number
+ FixedPcdGet32 (PcdPciBusMax) // End Bus Number
+ },
+ // CCIX ECAM
+ {
+ FixedPcdGet64 (PcdCcixExpressBaseAddress), // Base Address
+ 0x1, // Segment Group Number
+ FixedPcdGet32 (PcdCcixBusMin), // Start Bus Number
+ FixedPcdGet32 (PcdCcixBusMax) // End Bus Number
+ }
},
};
@@ -81,6 +416,167 @@ EDKII_PLATFORM_REPOSITORY_INFO MorelloRepositoryInfo = {
&MorelloSocRepositoryInfo
};
+/** Return a device Id mapping array.
+
+ @param [in] This Pointer to the Configuration Manager Protocol.
+ @param [in] CmObjectId The Configuration Manager Object ID.
+ @param [in] Token A token for identifying the object
+ @param [in, out] CmObject Pointer to the Configuration Manager Object
+ descriptor describing the requested Object.
+
+ @retval EFI_SUCCESS Success.
+ @retval EFI_INVALID_PARAMETER A parameter is invalid.
+ @retval EFI_NOT_FOUND The required object information is not found.
+**/
+EFI_STATUS
+EFIAPI
+GetDeviceIdMappingArray (
+ IN CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL *CONST This,
+ IN CONST CM_OBJECT_ID CmObjectId,
+ IN CONST CM_OBJECT_TOKEN Token,
+ IN OUT CM_OBJ_DESCRIPTOR *CONST CmObject
+ )
+{
+ EDKII_SOC_PLATFORM_REPOSITORY_INFO *PlatformRepo;
+ UINTN Count;
+
+ if ((This == NULL) || (CmObject == NULL)) {
+ ASSERT (This != NULL);
+ ASSERT (CmObject != NULL);
+ return EFI_INVALID_PARAMETER;
+ }
+
+ PlatformRepo = This->PlatRepoInfo->SocPlatRepoInfo;
+
+ DEBUG ((DEBUG_INFO, "DeviceIdMapping - Token = %p\n"));
+
+ if (Token == (CM_OBJECT_TOKEN)&PlatformRepo->DeviceIdMapping[0][0]) {
+ Count = 2;
+ DEBUG ((DEBUG_INFO, "DeviceIdMapping - Found DeviceIdMapping[0][0]\n"));
+ } else if (Token ==
+ (CM_OBJECT_TOKEN)&PlatformRepo->DeviceIdMapping[1][0])
+ {
+ Count = 1;
+ DEBUG ((DEBUG_INFO, "DeviceIdMapping - Found DeviceIdMapping[1][0]\n"));
+ } else if (Token ==
+ (CM_OBJECT_TOKEN)&PlatformRepo->DeviceIdMapping[1][1])
+ {
+ Count = 1;
+ DEBUG ((DEBUG_INFO, "DeviceIdMapping - Found DeviceIdMapping[1][1]\n"));
+ } else if (Token ==
+ (CM_OBJECT_TOKEN)&PlatformRepo->DeviceIdMapping[2][0])
+ {
+ Count = 2;
+ DEBUG ((DEBUG_INFO, "DeviceIdMapping - Found DeviceIdMapping[2][0]\n"));
+ } else {
+ DEBUG ((DEBUG_INFO, "DeviceIdMapping - Not Found\n"));
+ return EFI_NOT_FOUND;
+ }
+
+ CmObject->Data = (VOID *)Token;
+ CmObject->ObjectId = CmObjectId;
+ CmObject->Count = Count;
+ CmObject->Size = Count * sizeof (CM_ARM_ID_MAPPING);
+
+ return EFI_SUCCESS;
+}
+
+/** Return an ITS identifier array.
+
+ @param [in] This Pointer to the Configuration Manager Protocol.
+ @param [in] CmObjectId The Configuration Manager Object ID.
+ @param [in] Token A token for identifying the object
+ @param [in, out] CmObject Pointer to the Configuration Manager Object
+ descriptor describing the requested Object.
+
+ @retval EFI_SUCCESS Success.
+ @retval EFI_INVALID_PARAMETER A parameter is invalid.
+ @retval EFI_NOT_FOUND The required object information is not found.
+**/
+EFI_STATUS
+EFIAPI
+GetItsIdentifierArray (
+ IN CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL *CONST This,
+ IN CONST CM_OBJECT_ID CmObjectId,
+ IN CONST CM_OBJECT_TOKEN Token,
+ IN OUT CM_OBJ_DESCRIPTOR *CONST CmObject
+ )
+{
+ EDKII_SOC_PLATFORM_REPOSITORY_INFO *PlatformRepo;
+ UINTN Count;
+ UINTN Index;
+
+ if ((This == NULL) || (CmObject == NULL)) {
+ ASSERT (This != NULL);
+ ASSERT (CmObject != NULL);
+ return EFI_INVALID_PARAMETER;
+ }
+
+ PlatformRepo = This->PlatRepoInfo->SocPlatRepoInfo;
+
+ Count = ARRAY_SIZE (PlatformRepo->ItsIdentifierArray);
+
+ for (Index = 0; Index < Count; Index++) {
+ if (Token == (CM_OBJECT_TOKEN)&PlatformRepo->ItsIdentifierArray[Index]) {
+ CmObject->ObjectId = CmObjectId;
+ CmObject->Size = sizeof (PlatformRepo->ItsIdentifierArray[0]);
+ CmObject->Data = (VOID *)&PlatformRepo->ItsIdentifierArray[Index];
+ CmObject->Count = 1;
+ return EFI_SUCCESS;
+ }
+ }
+
+ return EFI_NOT_FOUND;
+}
+
+/** Return an ITS group info.
+
+ @param [in] This Pointer to the Configuration Manager Protocol.
+ @param [in] CmObjectId The Configuration Manager Object ID.
+ @param [in] Token A token for identifying the object
+ @param [in, out] CmObject Pointer to the Configuration Manager Object
+ descriptor describing the requested Object.
+
+ @retval EFI_SUCCESS Success.
+ @retval EFI_INVALID_PARAMETER A parameter is invalid.
+ @retval EFI_NOT_FOUND The required object information is not found.
+**/
+EFI_STATUS
+EFIAPI
+GetItsGroupInfo (
+ IN CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL *CONST This,
+ IN CONST CM_OBJECT_ID CmObjectId,
+ IN CONST CM_OBJECT_TOKEN Token,
+ IN OUT CM_OBJ_DESCRIPTOR *CONST CmObject
+ )
+{
+ EDKII_SOC_PLATFORM_REPOSITORY_INFO *PlatformRepo;
+ UINTN Count;
+ UINTN Index;
+
+ if ((This == NULL) || (CmObject == NULL)) {
+ ASSERT (This != NULL);
+ ASSERT (CmObject != NULL);
+ return EFI_INVALID_PARAMETER;
+ }
+
+ PlatformRepo = This->PlatRepoInfo->SocPlatRepoInfo;
+
+ Count = ARRAY_SIZE (PlatformRepo->ItsGroupInfo);
+
+ for (Index = 0; Index < Count; Index++) {
+ if (Token == (CM_OBJECT_TOKEN)&PlatformRepo->ItsGroupInfo[Index]) {
+ CmObject->ObjectId = CmObjectId;
+ CmObject->Size = sizeof (PlatformRepo->ItsGroupInfo[0]);
+ CmObject->Data = (VOID *)&PlatformRepo->ItsGroupInfo[Index];
+ CmObject->Count = 1;
+ return EFI_SUCCESS;
+ }
+ }
+
+ return EFI_NOT_FOUND;
+}
+
/** Return platform specific ARM namespace object.
@param [in] This Pointer to the Configuration Manager Protocol.
@@ -103,7 +599,105 @@ GetArmNameSpaceObjectPlat (
IN OUT CM_OBJ_DESCRIPTOR *CONST CmObject
)
{
- return EFI_NOT_FOUND;
+ EFI_STATUS Status;
+ EDKII_SOC_PLATFORM_REPOSITORY_INFO *PlatformRepo;
+
+ if ((This == NULL) || (CmObject == NULL)) {
+ ASSERT (This != NULL);
+ ASSERT (CmObject != NULL);
+ return EFI_INVALID_PARAMETER;
+ }
+
+ PlatformRepo = This->PlatRepoInfo->SocPlatRepoInfo;
+ Status = EFI_NOT_FOUND;
+
+ switch (GET_CM_OBJECT_ID (CmObjectId)) {
+ case EArmObjGicItsInfo:
+ Status = HandleCmObject (
+ CmObjectId,
+ &PlatformRepo->GicItsInfo,
+ sizeof (PlatformRepo->GicItsInfo),
+ ARRAY_SIZE (PlatformRepo->GicItsInfo),
+ CmObject
+ );
+ break;
+
+ case EArmObjSmmuV3:
+ Status = HandleCmObject (
+ CmObjectId,
+ PlatformRepo->SmmuV3Info,
+ sizeof (PlatformRepo->SmmuV3Info),
+ ARRAY_SIZE (PlatformRepo->SmmuV3Info),
+ CmObject
+ );
+ break;
+
+ case EArmObjItsGroup:
+ Status = HandleCmObjectRefByToken (
+ This,
+ CmObjectId,
+ PlatformRepo->ItsGroupInfo,
+ sizeof (PlatformRepo->ItsGroupInfo),
+ ARRAY_SIZE (PlatformRepo->ItsGroupInfo),
+ Token,
+ GetItsGroupInfo,
+ CmObject
+ );
+ break;
+
+ case EArmObjGicItsIdentifierArray:
+ Status = HandleCmObjectRefByToken (
+ This,
+ CmObjectId,
+ PlatformRepo->ItsIdentifierArray,
+ sizeof (PlatformRepo->ItsIdentifierArray),
+ ARRAY_SIZE (PlatformRepo->ItsIdentifierArray),
+ Token,
+ GetItsIdentifierArray,
+ CmObject
+ );
+ break;
+
+ case EArmObjRootComplex:
+ Status = HandleCmObject (
+ CmObjectId,
+ PlatformRepo->RootComplexInfo,
+ sizeof (PlatformRepo->RootComplexInfo),
+ ARRAY_SIZE (PlatformRepo->RootComplexInfo),
+ CmObject
+ );
+ break;
+
+ case EArmObjIdMappingArray:
+ Status = HandleCmObjectRefByToken (
+ This,
+ CmObjectId,
+ PlatformRepo->DeviceIdMapping,
+ sizeof (PlatformRepo->DeviceIdMapping),
+ ARRAY_SIZE (PlatformRepo->DeviceIdMapping),
+ Token,
+ GetDeviceIdMappingArray,
+ CmObject
+ );
+ break;
+
+ case EArmObjPciConfigSpaceInfo:
+ Status = HandleCmObject (
+ CmObjectId,
+ PlatformRepo->PciConfigInfo,
+ sizeof (PlatformRepo->PciConfigInfo),
+ ARRAY_SIZE (PlatformRepo->PciConfigInfo),
+ CmObject
+ );
+ break;
+
+ default:
+ {
+ break;
+ }
+ }// switch
+
+ return Status;
}
/** Return platform specific standard namespace object.
diff --git
a/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/AslTables/SsdtPciSoc.asl
b/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/AslTables/SsdtPciSoc.asl
new file mode 100644
index 000000000000..32b78aa53aff
--- /dev/null
+++
b/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/AslTables/SsdtPciSoc.asl
@@ -0,0 +1,223 @@
+/** @file
+ Secondary System Description Table (SSDT)
+
+ Copyright (c) 2021, ARM Limited. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Reference(s):
+ - ACPI for Arm Components 1.0, Platform Design Document
+
+**/
+
+#include "ConfigurationManager.h"
+
+#define LNK_DEVICE(Unique_Id, Link_Name, irq) \
+ Device(Link_Name) { \
+ Name(_HID, EISAID("PNP0C0F")) \
+ Name(_UID, Unique_Id) \
+ Name(_PRS, ResourceTemplate() { \
+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { irq } \
+ }) \
+ Method (_CRS, 0) { Return (_PRS) } \
+ Method (_SRS, 1) { } \
+ Method (_DIS) { } \
+}
+
+#define PRT_ENTRY(Address, Pin, Link)
\
+ Package (4) {
\
+ Address, /* uses the same format as _ADR */
\
+ Pin, /* The PCI pin number of the device (0-INTA, 1-INTB, 2-INTC,
3-INTD) */ \
+ Link, /* Interrupt allocated via Link device */
\
+ Zero /* global system interrupt number (no used) */
\
+}
+
+#define ROOT_PRT_ENTRY(Pin, Link) PRT_ENTRY(0x0000FFFF, Pin, Link) //
Device 0 for Bridge.
+
+DefinitionBlock("SsdtPci.aml", "SSDT", 1, "ARMLTD", "MORELLO",
+ CFG_MGR_OEM_REVISION)
+{
+ Scope (_SB) {
+ // PCI Root Complex
+ LNK_DEVICE(1, LNKA, 201)
+ LNK_DEVICE(2, LNKB, 202)
+ LNK_DEVICE(3, LNKC, 203)
+ LNK_DEVICE(4, LNKD, 204)
+
+ // CCIX Root Complex
+ LNK_DEVICE(1, LNKE, 233)
+ LNK_DEVICE(2, LNKF, 234)
+ LNK_DEVICE(3, LNKG, 235)
+ LNK_DEVICE(4, LNKH, 236)
+
+ // PCI Root Complex
+ Device(PCI0) {
+ Name (_HID, EISAID("PNP0A08")) // PCI Express Root Bridge
+ Name (_CID, EISAID("PNP0A03")) // Compatible PCI Root Bridge
+ Name (_SEG, Zero) // PCI Segment Group number
+ Name (_BBN, Zero) // PCI Base Bus Number
+ Name (_CCA, 1) // Cache Coherency Attribute
+
+ // Root Complex 0
+ Device (RP0) {
+ Name(_ADR, 0xF0000000) // Dev 0, Func 0
+ }
+
+ // PCI Routing Table
+ Name(_PRT, Package() {
+ ROOT_PRT_ENTRY(0, LNKA), // INTA
+ ROOT_PRT_ENTRY(1, LNKB), // INTB
+ ROOT_PRT_ENTRY(2, LNKC), // INTC
+ ROOT_PRT_ENTRY(3, LNKD), // INTD
+ })
+
+ // Root complex resources
+ Method (_CRS, 0, Serialized) {
+ Name (RBUF, ResourceTemplate () {
+ WordBusNumber ( // Bus numbers assigned
to this root
+ ResourceProducer,
+ MinFixed,
+ MaxFixed,
+ PosDecode,
+ 0, // AddressGranularity
+ FixedPcdGet32 (PcdPciBusMin), // AddressMinimum -
Minimum Bus Number
+ FixedPcdGet32 (PcdPciBusMax), // AddressMaximum -
Maximum Bus Number
+ 0, // AddressTranslation -
Set to 0
+ FixedPcdGet32 (PcdPciBusCount) // RangeLength - Number
of Busses
+ )
+
+ DWordMemory ( // 32-bit BAR Windows
+ ResourceProducer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ Cacheable,
+ ReadWrite,
+ 0x00000000, // Granularity
+ FixedPcdGet32 (PcdPciMmio32Base), // Min Base Address
+ FixedPcdGet32 (PcdPciMmio32MaxBase), // Max Base Address
+ FixedPcdGet32 (PcdPciMmio32Translation), // Translate
+ FixedPcdGet32 (PcdPciMmio32Size) // Length
+ )
+
+ QWordMemory ( // 64-bit BAR Windows
+ ResourceProducer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ Cacheable,
+ ReadWrite,
+ 0x00000000, // Granularity
+ FixedPcdGet64 (PcdPciMmio64Base), // Min Base Address
+ FixedPcdGet64 (PcdPciMmio64MaxBase), // Max Base Address
+ FixedPcdGet64 (PcdPciMmio64Translation), // Translate
+ FixedPcdGet64 (PcdPciMmio64Size) // Length
+ )
+
+ DWordIo ( // IO window
+ ResourceProducer,
+ MinFixed,
+ MaxFixed,
+ PosDecode,
+ EntireRange,
+ 0x00000000, // Granularity
+ FixedPcdGet32 (PcdPciIoBase), // Min Base Address
+ FixedPcdGet32 (PcdPciIoMaxBase), // Max Base Address
+ FixedPcdGet32 (PcdPciIoTranslation), // Translate
+ FixedPcdGet32 (PcdPciIoSize), // Length
+ ,
+ ,
+ ,
+ TypeTranslation
+ )
+ }) // Name(RBUF)
+ Return (RBUF)
+ } // Method (_CRS)
+ } // Device (PCI0)
+
+ // CCIX Root Complex
+ Device(PCI1) {
+ Name (_HID, EISAID("PNP0A08")) // PCI Express Root Bridge
+ Name (_CID, EISAID("PNP0A03")) // Compatible PCI Root Bridge
+ Name (_SEG, 1) // PCI Segment Group number
+ Name (_BBN, 0) // PCI Base Bus Number
+ Name (_CCA, 1) // Cache Coherency Attribute
+
+ // Root Complex 1
+ Device (RP1) {
+ Name(_ADR, 0xF0000000) // Dev 0, Func 0
+ }
+
+ // PCI Routing Table
+ Name(_PRT, Package() {
+ ROOT_PRT_ENTRY(0, LNKE), // INTA
+ ROOT_PRT_ENTRY(1, LNKF), // INTB
+ ROOT_PRT_ENTRY(2, LNKG), // INTC
+ ROOT_PRT_ENTRY(3, LNKH), // INTD
+ })
+
+ // Root complex resources
+ Method (_CRS, 0, Serialized) {
+ Name (RBUF, ResourceTemplate () {
+ WordBusNumber ( // Bus numbers assigned
to this root
+ ResourceProducer,
+ MinFixed,
+ MaxFixed,
+ PosDecode,
+ 0, // AddressGranularity
+ FixedPcdGet32 (PcdCcixBusMin), // AddressMinimum -
Minimum Bus Number
+ FixedPcdGet32 (PcdCcixBusMax), // AddressMaximum -
Maximum Bus Number
+ 0, // AddressTranslation -
Set to 0
+ FixedPcdGet32 (PcdCcixBusCount) // RangeLength - Number
of Busses
+ )
+
+ DWordMemory ( // 32-bit BAR Windows
+ ResourceProducer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ Cacheable,
+ ReadWrite,
+ 0x00000000, // Granularity
+ FixedPcdGet32 (PcdCcixMmio32Base), // Min Base Address
+ FixedPcdGet32 (PcdCcixMmio32MaxBase), // Max Base Address
+ FixedPcdGet32 (PcdCcixMmio32Translation), // Translate
+ FixedPcdGet32 (PcdCcixMmio32Size) // Length
+ )
+
+ QWordMemory ( // 64-bit BAR Windows
+ ResourceProducer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ Cacheable,
+ ReadWrite,
+ 0x00000000, // Granularity
+ FixedPcdGet64 (PcdCcixMmio64Base), // Min Base Address
+ FixedPcdGet64 (PcdCcixMmio64MaxBase), // Max Base Address
+ FixedPcdGet64 (PcdCcixMmio64Translation), // Translate
+ FixedPcdGet64 (PcdCcixMmio64Size) // Length
+ )
+
+ DWordIo ( // IO window
+ ResourceProducer,
+ MinFixed,
+ MaxFixed,
+ PosDecode,
+ EntireRange,
+ 0x00000000, // Granularity
+ FixedPcdGet32 (PcdCcixIoBase), // Min Base Address
+ FixedPcdGet32 (PcdCcixIoMaxBase), // Max Base Address
+ FixedPcdGet32 (PcdCcixIoTranslation), // Translate
+ FixedPcdGet32 (PcdCcixIoSize), // Length
+ ,
+ ,
+ ,
+ TypeTranslation
+ )
+ }) // Name(RBUF)
+ Return (RBUF)
+ } // Method (_CRS)
+ } // Device (PCI1)
+ } // _SB
+} // DB
--
2.17.1
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