From: Anurag Koul <anurag.k...@arm.com>
Add definitions for both PCIe and CCIX Root Complex in PciHostBridge
Library. Also, use platform-specific PCI Segment Library and PCI
Express Library to enable PCIe support for Morello SoC.
With PCIe support added, various other modules dependent on PCIe
for instance, USB, AHCI, SATA, NVMe, etc., have also been enabled in
the platform definition files.
Signed-off-by: Anurag Koul <anurag.k...@arm.com>
Signed-off-by: Chandni Cherukuri <chandni.cheruk...@arm.com>
---
Platform/ARM/Morello/MorelloPlatform.dec | 46
++--
Platform/ARM/Morello/MorelloPlatform.dsc.inc | 17 ++
Platform/ARM/Morello/MorelloPlatformFvp.dsc | 21 +-
Platform/ARM/Morello/MorelloPlatformSoc.dsc | 27 +++
Platform/ARM/Morello/MorelloPlatformSoc.fdf | 25 ++
Platform/ARM/Morello/Library/PciHostBridgeLib/PciHostBridgeLibSoc.inf | 57
+++++
Platform/ARM/Morello/Library/PlatformLib/PlatformLibSoc.inf | 18 ++
Platform/ARM/Morello/Library/PciHostBridgeLib/PciHostBridgeLibSoc.c | 247
++++++++++++++++++++
Platform/ARM/Morello/Library/PlatformLib/PlatformLibMemSoc.c | 50
+++-
9 files changed, 479 insertions(+), 29 deletions(-)
diff --git a/Platform/ARM/Morello/MorelloPlatform.dec
b/Platform/ARM/Morello/MorelloPlatform.dec
index 6f5c1c1b59fc..07701e7611b8 100644
--- a/Platform/ARM/Morello/MorelloPlatform.dec
+++ b/Platform/ARM/Morello/MorelloPlatform.dec
@@ -39,28 +39,46 @@
# PCIe
gArmMorelloTokenSpaceGuid.PcdPciBusMin|0|UINT32|0x00000009
- gArmMorelloTokenSpaceGuid.PcdPciBusMax|15|UINT32|0x0000000A
- gArmMorelloTokenSpaceGuid.PcdPciBusCount|16|UINT32|0x0000000B
+ gArmMorelloTokenSpaceGuid.PcdPciBusMax|255|UINT32|0x0000000A
+ gArmMorelloTokenSpaceGuid.PcdPciBusCount|256|UINT32|0x0000000B
gArmMorelloTokenSpaceGuid.PcdPciIoBase|0x0|UINT32|0x0000000C
- gArmMorelloTokenSpaceGuid.PcdPciIoSize|0x00800000|UINT32|0x0000000D
- gArmMorelloTokenSpaceGuid.PcdPciIoMaxBase|0x007FFFFF|UINT32|0x0000000E
- gArmMorelloTokenSpaceGuid.PcdPciIoTranslation|0x67800000|UINT32|0x0000000F
+ gArmMorelloTokenSpaceGuid.PcdPciIoSize|0x00400000|UINT32|0x0000000D
+ gArmMorelloTokenSpaceGuid.PcdPciIoMaxBase|0x003FFFFF|UINT32|0x0000000E
+ gArmMorelloTokenSpaceGuid.PcdPciIoTranslation|0x6F000000|UINT32|0x0000000F
gArmMorelloTokenSpaceGuid.PcdPciMmio32Base|0x60000000|UINT32|0x00000010
- gArmMorelloTokenSpaceGuid.PcdPciMmio32Size|0x07800000|UINT32|0x00000011
- gArmMorelloTokenSpaceGuid.PcdPciMmio32MaxBase|0x677FFFFF|UINT32|0x00000012
+ gArmMorelloTokenSpaceGuid.PcdPciMmio32Size|0x0F000000|UINT32|0x00000011
+ gArmMorelloTokenSpaceGuid.PcdPciMmio32MaxBase|0x6EFFFFFF|UINT32|0x00000012
gArmMorelloTokenSpaceGuid.PcdPciMmio32Translation|0x0|UINT32|0x00000013
gArmMorelloTokenSpaceGuid.PcdPciMmio64Base|0x900000000|UINT64|0x00000014
- gArmMorelloTokenSpaceGuid.PcdPciMmio64Size|0x2000000000|UINT64|0x00000015
- gArmMorelloTokenSpaceGuid.PcdPciMmio64MaxBase|0x28FFFFFFFF|UINT64|0x00000016
+ gArmMorelloTokenSpaceGuid.PcdPciMmio64Size|0x1FC0000000|UINT64|0x00000015
+ gArmMorelloTokenSpaceGuid.PcdPciMmio64MaxBase|0x28BFFFFFFF|UINT64|0x00000016
gArmMorelloTokenSpaceGuid.PcdPciMmio64Translation|0x0|UINT64|0x00000017
-
gArmMorelloTokenSpaceGuid.PcdPciExpressBaseAddress|0x20000000|UINT64|0x00000018
+
gArmMorelloTokenSpaceGuid.PcdPciExpressBaseAddress|0x28C0000000|UINT64|0x00000018
+
+ # CCIX
+ gArmMorelloTokenSpaceGuid.PcdCcixBusMin|0|UINT32|0x0000019
+ gArmMorelloTokenSpaceGuid.PcdCcixBusMax|255|UINT32|0x000001A
+ gArmMorelloTokenSpaceGuid.PcdCcixBusCount|256|UINT32|0x000001B
+ gArmMorelloTokenSpaceGuid.PcdCcixIoBase|0x0|UINT32|0x000001C
+ gArmMorelloTokenSpaceGuid.PcdCcixIoSize|0x0400000|UINT32|0x000001D
+ gArmMorelloTokenSpaceGuid.PcdCcixIoMaxBase|0x003FFFFF|UINT32|0x000001E
+ gArmMorelloTokenSpaceGuid.PcdCcixIoTranslation|0x7F000000|UINT32|0x00000001F
+ gArmMorelloTokenSpaceGuid.PcdCcixMmio32Base|0x70000000|UINT32|0x00000020
+ gArmMorelloTokenSpaceGuid.PcdCcixMmio32Size|0x0F000000|UINT32|0x00000021
+ gArmMorelloTokenSpaceGuid.PcdCcixMmio32MaxBase|0x7EFFFFFF|UINT32|0x000000022
+ gArmMorelloTokenSpaceGuid.PcdCcixMmio32Translation|0x0|UINT32|0x00000023
+ gArmMorelloTokenSpaceGuid.PcdCcixMmio64Base|0x3000000000|UINT64|0x00000024
+ gArmMorelloTokenSpaceGuid.PcdCcixMmio64Size|0x1FC0000000|UINT64|0x00000025
+ gArmMorelloTokenSpaceGuid.PcdCcixMmio64MaxBase|0x4FBFFFFFFF|UINT64|0x00000026
+ gArmMorelloTokenSpaceGuid.PcdCcixMmio64Translation|0x0|UINT64|0x00000027
+
gArmMorelloTokenSpaceGuid.PcdCcixExpressBaseAddress|0x4FC0000000|UINT64|0x0000028
# Virtio Net device
-
gArmMorelloTokenSpaceGuid.PcdVirtioNetBaseAddress|0x00000000|UINT32|0x00000019
- gArmMorelloTokenSpaceGuid.PcdVirtioNetSize|0x00000000|UINT32|0x0000001A
- gArmMorelloTokenSpaceGuid.PcdVirtioNetInterrupt|0x00000000|UINT32|0x0000001B
+
gArmMorelloTokenSpaceGuid.PcdVirtioNetBaseAddress|0x00000000|UINT32|0x00000029
+ gArmMorelloTokenSpaceGuid.PcdVirtioNetSize|0x00000000|UINT32|0x0000002A
+ gArmMorelloTokenSpaceGuid.PcdVirtioNetInterrupt|0x00000000|UINT32|0x0000002B
[PcdsFeatureFlag.common]
gArmMorelloTokenSpaceGuid.PcdRamDiskSupported|FALSE|BOOLEAN|0x00000007
gArmMorelloTokenSpaceGuid.PcdVirtioBlkSupported|FALSE|BOOLEAN|0x00000008
- gArmMorelloTokenSpaceGuid.PcdVirtioNetSupported|FALSE|BOOLEAN|0x0000001C
+ gArmMorelloTokenSpaceGuid.PcdVirtioNetSupported|FALSE|BOOLEAN|0x0000002C
diff --git a/Platform/ARM/Morello/MorelloPlatform.dsc.inc
b/Platform/ARM/Morello/MorelloPlatform.dsc.inc
index 862d5f2da1b0..e855c1ba0350 100644
--- a/Platform/ARM/Morello/MorelloPlatform.dsc.inc
+++ b/Platform/ARM/Morello/MorelloPlatform.dsc.inc
@@ -209,3 +209,20 @@
# RAM Disk
MdeModulePkg/Universal/Disk/RamDiskDxe/RamDiskDxe.inf
+
+ # Required by PCI
+ ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf
+
+ # PCI Support
+ MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
+ MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf {
+ <PcdsFixedAtBuild>
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x8010004F
+ }
+
+ # AHCI Support
+ MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
+ MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
+
+ # SATA Controller
+ MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf
diff --git a/Platform/ARM/Morello/MorelloPlatformFvp.dsc
b/Platform/ARM/Morello/MorelloPlatformFvp.dsc
index 1f9199fba2dc..61f54b891059 100644
--- a/Platform/ARM/Morello/MorelloPlatformFvp.dsc
+++ b/Platform/ARM/Morello/MorelloPlatformFvp.dsc
@@ -72,6 +72,13 @@
gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSupport|FALSE
gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x20000000
+ #FVP Specific PCD values for PCIe
+ gArmMorelloTokenSpaceGuid.PcdPciBusMax|15
+ gArmMorelloTokenSpaceGuid.PcdPciBusCount|16
+ gArmMorelloTokenSpaceGuid.PcdPciMmio64Size|0x2000000000
+ gArmMorelloTokenSpaceGuid.PcdPciMmio64MaxBase|0x28FFFFFFFF
+ gArmMorelloTokenSpaceGuid.PcdPciExpressBaseAddress|0x20000000
+
[Components.common]
OvmfPkg/VirtioBlkDxe/VirtioBlk.inf
OvmfPkg/VirtioNetDxe/VirtioNet.inf
@@ -81,17 +88,3 @@
# Required by PCI
ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf
-
- # PCI Support
- MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
- MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf {
- <PcdsFixedAtBuild>
- gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x8010004F
- }
-
- # AHCI Support
- MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
- MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
-
- # SATA Controller
- MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf
diff --git a/Platform/ARM/Morello/MorelloPlatformSoc.dsc
b/Platform/ARM/Morello/MorelloPlatformSoc.dsc
index 8335c50803b3..b6fe74ec6fdd 100644
--- a/Platform/ARM/Morello/MorelloPlatformSoc.dsc
+++ b/Platform/ARM/Morello/MorelloPlatformSoc.dsc
@@ -42,6 +42,33 @@
# Platform Library
ArmPlatformLib|Platform/ARM/Morello/Library/PlatformLib/PlatformLibSoc.inf
+ #USB Requirement
+ UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf
+
+ [LibraryClasses.common.DXE_DRIVER]
+
PciHostBridgeLib|Platform/ARM/Morello/Library/PciHostBridgeLib/PciHostBridgeLibSoc.inf
+ FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf
+ PciSegmentLib|Platform/ARM/Morello/Library/PciSegmentLib/PciSegmentLib.inf
+ PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf
+ PciExpressLib|Platform/ARM/Morello/Library/PciExpressLib/PciExpressLib.inf
+
+[PcdsFixedAtBuild.common]
+ # PCIe
+ gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize|24
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSupport|FALSE
+
[Components.common]
# Platform driver
Platform/ARM/Morello/Drivers/PlatformDxe/PlatformDxeSoc.inf
+
+ # Usb Support
+ MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf
+ MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
+ MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
+ MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
+ MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
+ MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
+
+ # NVMe boot devices
+ MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
+
diff --git a/Platform/ARM/Morello/MorelloPlatformSoc.fdf
b/Platform/ARM/Morello/MorelloPlatformSoc.fdf
index e7d4a6a9828d..ec0297fdbca6 100644
--- a/Platform/ARM/Morello/MorelloPlatformSoc.fdf
+++ b/Platform/ARM/Morello/MorelloPlatformSoc.fdf
@@ -141,6 +141,31 @@ READ_LOCK_STATUS = TRUE
INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
+ # Required by PCI
+ INF ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf
+
+ # PCI Support
+ INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
+ INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
+
+ # AHCI Support
+ INF MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
+ INF MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
+
+ # SATA Controller
+ INF MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf
+
+ # Usb Support
+ INF MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf
+ INF MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
+ INF MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
+ INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
+ INF MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
+ INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
+
+ # NVMe boot devices
+ INF MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
+
[FV.FVMAIN_COMPACT]
FvAlignment = 8
BlockSize = 0x1000
diff --git
a/Platform/ARM/Morello/Library/PciHostBridgeLib/PciHostBridgeLibSoc.inf
b/Platform/ARM/Morello/Library/PciHostBridgeLib/PciHostBridgeLibSoc.inf
new file mode 100644
index 000000000000..3187e4b34087
--- /dev/null
+++ b/Platform/ARM/Morello/Library/PciHostBridgeLib/PciHostBridgeLibSoc.inf
@@ -0,0 +1,57 @@
+## @file
+# PCI Host Bridge Library instance for ARM Morello SoC platform.
+#
+# Copyright (c) 2021, ARM Limited. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001B
+ BASE_NAME = PciHostBridgeLib
+ FILE_GUID = 82f5bd18-4e07-11ec-81d3-0242ac130003
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = PciHostBridgeLib|DXE_DRIVER
+
+#
+# The following information is for reference only and not required by the build
+# tools.
+#
+# VALID_ARCHITECTURES = AARCH64
+#
+
+[Sources]
+ PciHostBridgeLibSoc.c
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+ Platform/ARM/Morello/MorelloPlatform.dec
+
+[FixedPcd]
+ gArmMorelloTokenSpaceGuid.PcdPciBusMax
+ gArmMorelloTokenSpaceGuid.PcdPciBusMin
+ gArmMorelloTokenSpaceGuid.PcdPciIoBase
+ gArmMorelloTokenSpaceGuid.PcdPciIoSize
+ gArmMorelloTokenSpaceGuid.PcdPciMmio32Base
+ gArmMorelloTokenSpaceGuid.PcdPciMmio32Size
+ gArmMorelloTokenSpaceGuid.PcdPciMmio64Base
+ gArmMorelloTokenSpaceGuid.PcdPciMmio64Size
+
+ gArmMorelloTokenSpaceGuid.PcdCcixBusMin
+ gArmMorelloTokenSpaceGuid.PcdCcixBusMax
+ gArmMorelloTokenSpaceGuid.PcdCcixIoBase
+ gArmMorelloTokenSpaceGuid.PcdCcixIoSize
+ gArmMorelloTokenSpaceGuid.PcdCcixMmio32Base
+ gArmMorelloTokenSpaceGuid.PcdCcixMmio32Size
+ gArmMorelloTokenSpaceGuid.PcdCcixMmio64Base
+ gArmMorelloTokenSpaceGuid.PcdCcixMmio64Size
+
+[Protocols]
+ gEfiCpuIo2ProtocolGuid ## CONSUMES
+
+[Depex]
+ gEfiCpuIo2ProtocolGuid
diff --git a/Platform/ARM/Morello/Library/PlatformLib/PlatformLibSoc.inf
b/Platform/ARM/Morello/Library/PlatformLib/PlatformLibSoc.inf
index bc31b8709152..0a36a5fe50a5 100644
--- a/Platform/ARM/Morello/Library/PlatformLib/PlatformLibSoc.inf
+++ b/Platform/ARM/Morello/Library/PlatformLib/PlatformLibSoc.inf
@@ -32,6 +32,24 @@
[FixedPcd]
gArmMorelloTokenSpaceGuid.PcdDramBlock2Base
+ gArmMorelloTokenSpaceGuid.PcdPciBusMax
+ gArmMorelloTokenSpaceGuid.PcdPciBusMin
+ gArmMorelloTokenSpaceGuid.PcdPciExpressBaseAddress
+ gArmMorelloTokenSpaceGuid.PcdPciIoSize
+ gArmMorelloTokenSpaceGuid.PcdPciMmio32Base
+ gArmMorelloTokenSpaceGuid.PcdPciMmio32Size
+ gArmMorelloTokenSpaceGuid.PcdPciMmio64Base
+ gArmMorelloTokenSpaceGuid.PcdPciMmio64Size
+
+ gArmMorelloTokenSpaceGuid.PcdCcixBusMax
+ gArmMorelloTokenSpaceGuid.PcdCcixBusMin
+ gArmMorelloTokenSpaceGuid.PcdCcixExpressBaseAddress
+ gArmMorelloTokenSpaceGuid.PcdCcixIoSize
+ gArmMorelloTokenSpaceGuid.PcdCcixMmio32Base
+ gArmMorelloTokenSpaceGuid.PcdCcixMmio32Size
+ gArmMorelloTokenSpaceGuid.PcdCcixMmio64Base
+ gArmMorelloTokenSpaceGuid.PcdCcixMmio64Size
+
gArmTokenSpaceGuid.PcdArmPrimaryCore
gArmTokenSpaceGuid.PcdArmPrimaryCoreMask
gArmTokenSpaceGuid.PcdSystemMemoryBase
diff --git
a/Platform/ARM/Morello/Library/PciHostBridgeLib/PciHostBridgeLibSoc.c
b/Platform/ARM/Morello/Library/PciHostBridgeLib/PciHostBridgeLibSoc.c
new file mode 100644
index 000000000000..4d97474821df
--- /dev/null
+++ b/Platform/ARM/Morello/Library/PciHostBridgeLib/PciHostBridgeLibSoc.c
@@ -0,0 +1,247 @@
+/** @file
+ PCI Host Bridge Library instance for ARM Morello SoC platform.
+
+ Copyright (c) 2021, ARM Limited. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <Library/DebugLib.h>
+#include <Library/DevicePathLib.h>
+#include <Library/PciHostBridgeLib.h>
+#include <Protocol/PciHostBridgeResourceAllocation.h>
+
+#define ROOT_COMPLEX_NUM 2
+
+GLOBAL_REMOVE_IF_UNREFERENCED
+STATIC CHAR16 CONST *CONST mPciHostBridgeLibAcpiAddressSpaceTypeStr[] = {
+ L"Mem", L"I/O", L"Bus"
+};
+
+#pragma pack(1)
+typedef struct {
+ ACPI_HID_DEVICE_PATH AcpiDevicePath;
+ EFI_DEVICE_PATH_PROTOCOL EndDevicePath;
+} EFI_PCI_ROOT_BRIDGE_DEVICE_PATH;
+#pragma pack ()
+
+STATIC EFI_PCI_ROOT_BRIDGE_DEVICE_PATH
mEfiPciRootBridgeDevicePath[ROOT_COMPLEX_NUM] = {
+ {
+ {
+ {
+ ACPI_DEVICE_PATH,
+ ACPI_DP,
+ {
+ (UINT8)sizeof (ACPI_HID_DEVICE_PATH),
+ (UINT8)(sizeof (ACPI_HID_DEVICE_PATH) >> 8)
+ }
+ },
+ EISA_PNP_ID (0x0A08),
+ 0
+ },
+ {
+ END_DEVICE_PATH_TYPE,
+ END_ENTIRE_DEVICE_PATH_SUBTYPE,
+ {
+ END_DEVICE_PATH_LENGTH,
+ 0
+ }
+ }
+ },
+ {
+ {
+ {
+ ACPI_DEVICE_PATH,
+ ACPI_DP,
+ {
+ (UINT8)sizeof (ACPI_HID_DEVICE_PATH),
+ (UINT8)(sizeof (ACPI_HID_DEVICE_PATH) >> 8)
+ }
+ },
+ EISA_PNP_ID (0x0A09),
+ 0
+ },
+ {
+ END_DEVICE_PATH_TYPE,
+ END_ENTIRE_DEVICE_PATH_SUBTYPE,
+ {
+ END_DEVICE_PATH_LENGTH,
+ 0
+ }
+ }
+ },
+};
+
+STATIC PCI_ROOT_BRIDGE mPciRootBridge[ROOT_COMPLEX_NUM] = {
+ {
+ 0, // Segment
+ 0, // Supports
+ 0, // Attributes
+ TRUE, // DmaAbove4G
+ FALSE, // NoExtendedConfigSpace
+ FALSE, // ResourceAssigned
+ EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM | // AllocationAttributes
+ EFI_PCI_HOST_BRIDGE_MEM64_DECODE,
+ {
+ // Bus
+ FixedPcdGet32 (PcdPciBusMin),
+ FixedPcdGet32 (PcdPciBusMax)
+ },{
+ // Io
+ FixedPcdGet64 (PcdPciIoBase),
+ FixedPcdGet64 (PcdPciIoBase) + FixedPcdGet64 (PcdPciIoSize) - 1
+ },{
+ // Mem
+ FixedPcdGet32 (PcdPciMmio32Base),
+ FixedPcdGet32 (PcdPciMmio32Base) + FixedPcdGet32 (PcdPciMmio32Size) - 1
+ },{
+ // MemAbove4G
+ FixedPcdGet64 (PcdPciMmio64Base),
+ FixedPcdGet64 (PcdPciMmio64Base) + FixedPcdGet64 (PcdPciMmio64Size) - 1
+ },{
+ // PMem
+ MAX_UINT64,
+ 0
+ },{
+ // PMemAbove4G
+ MAX_UINT64,
+ 0
+ },
+ (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[0]
+ },
+ {
+ 1, // Segment
+ 0, // Supports
+ 0, // Attributes
+ TRUE, // DmaAbove4G
+ FALSE, // NoExtendedConfigSpace
+ FALSE, // ResourceAssigned
+ EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM | // AllocationAttributes
+ EFI_PCI_HOST_BRIDGE_MEM64_DECODE,
+ {
+ // Bus
+ FixedPcdGet32 (PcdCcixBusMin),
+ FixedPcdGet32 (PcdCcixBusMax)
+ },{
+ // Io
+ FixedPcdGet64 (PcdCcixIoBase),
+ FixedPcdGet64 (PcdCcixIoBase) + FixedPcdGet64 (PcdCcixIoSize) - 1
+ },{
+ // Mem
+ FixedPcdGet32 (PcdCcixMmio32Base),
+ FixedPcdGet32 (PcdCcixMmio32Base) + FixedPcdGet32 (PcdCcixMmio32Size) - 1
+ },{
+ // MemAbove4G
+ FixedPcdGet64 (PcdCcixMmio64Base),
+ FixedPcdGet64 (PcdCcixMmio64Base) + FixedPcdGet64 (PcdCcixMmio64Size) - 1
+ },{
+ // PMem
+ MAX_UINT64,
+ 0
+ },{
+ // PMemAbove4G
+ MAX_UINT64,
+ 0
+ },
+ (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[1]
+ },
+};
+
+/**
+ Return all the root bridge instances in an array.
+
+ @param Count Return the count of root bridge instances.
+
+ @return All the root bridge instances in an array.
+ The array should be passed into PciHostBridgeFreeRootBridges()
+ when it's not used.
+**/
+PCI_ROOT_BRIDGE *
+EFIAPI
+PciHostBridgeGetRootBridges (
+ UINTN *Count
+ )
+{
+ *Count = ARRAY_SIZE (mPciRootBridge);
+ return mPciRootBridge;
+}
+
+/**
+ Free the root bridge instances array returned from
PciHostBridgeGetRootBridges().
+
+ @param Bridges The root bridge instances array.
+ @param Count The count of the array.
+**/
+VOID
+EFIAPI
+PciHostBridgeFreeRootBridges (
+ PCI_ROOT_BRIDGE *Bridges,
+ UINTN Count
+ )
+{
+}
+
+/**
+ Inform the platform that the resource conflict happens.
+
+ @param HostBridgeHandle Handle of the Host Bridge.
+ @param Configuration Pointer to PCI I/O and PCI memory resource
+ descriptors. The Configuration contains the resources
+ for all the root bridges. The resource for each root
+ bridge is terminated with END descriptor and an
+ additional END is appended indicating the end of the
+ entire resources. The resource descriptor field
+ values follow the description in
+ EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
+ .SubmitResources().
+**/
+VOID
+EFIAPI
+PciHostBridgeResourceConflict (
+ EFI_HANDLE HostBridgeHandle,
+ VOID *Configuration
+ )
+{
+ EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor;
+ UINTN RootBridgeIndex;
+
+ DEBUG ((DEBUG_ERROR, "PciHostBridge: Resource conflict happens!\n"));
+
+ RootBridgeIndex = 0;
+ Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Configuration;
+ while (Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR) {
+ DEBUG ((DEBUG_ERROR, "RootBridge[%d]:\n", RootBridgeIndex++));
+ for ( ; Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR; Descriptor++) {
+ ASSERT (
+ Descriptor->ResType <
+ (ARRAY_SIZE (mPciHostBridgeLibAcpiAddressSpaceTypeStr))
+ );
+ DEBUG ((
+ DEBUG_ERROR,
+ "%s: Length/Alignment = 0x%lx / 0x%lx\n",
+ mPciHostBridgeLibAcpiAddressSpaceTypeStr[Descriptor->ResType],
+ Descriptor->AddrLen,
+ Descriptor->AddrRangeMax
+ ));
+ if (Descriptor->ResType == ACPI_ADDRESS_SPACE_TYPE_MEM) {
+ DEBUG ((
+ DEBUG_ERROR,
+ "Granularity/SpecificFlag = %ld / %02x%s\n",
+ Descriptor->AddrSpaceGranularity,
+ Descriptor->SpecificFlag,
+ ((Descriptor->SpecificFlag &
+ EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE
+ ) != 0) ? L" (Prefetchable)" : L""
+ ));
+ }
+ }
+
+ //
+ // Skip the END descriptor for root bridge
+ //
+ ASSERT (Descriptor->Desc == ACPI_END_TAG_DESCRIPTOR);
+ Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)(
+ (EFI_ACPI_END_TAG_DESCRIPTOR *)Descriptor + 1
+ );
+ }
+}
diff --git a/Platform/ARM/Morello/Library/PlatformLib/PlatformLibMemSoc.c
b/Platform/ARM/Morello/Library/PlatformLib/PlatformLibMemSoc.c
index 67dd8469feb8..5140764c54bc 100644
--- a/Platform/ARM/Morello/Library/PlatformLib/PlatformLibMemSoc.c
+++ b/Platform/ARM/Morello/Library/PlatformLib/PlatformLibMemSoc.c
@@ -12,7 +12,7 @@
#include <MorelloPlatform.h>
// The total number of descriptors, including the final "end-of-table"
descriptor.
-#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 9
+#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 15
#if !defined (MDEPKG_NDEBUG)
STATIC CONST CHAR8 *gTblAttrDesc[] = {
@@ -163,6 +163,54 @@ ArmPlatformGetVirtualMemoryMap (
VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
LOG_MEM ("Expansion Peripherals : 0x%016lx - 0x%016lx [ 0x%016lx ]
{ %a }\n");
+ // PCIe ECAM Configuration Space
+ VirtualMemoryTable[++Index].PhysicalBase = PcdGet64
(PcdPciExpressBaseAddress);
+ VirtualMemoryTable[Index].VirtualBase = PcdGet64
(PcdPciExpressBaseAddress);
+ VirtualMemoryTable[Index].Length = (FixedPcdGet32 (PcdPciBusMax) -
+ FixedPcdGet32 (PcdPciBusMin) + 1) *
+ SIZE_1MB;
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+ LOG_MEM ("PCIe ECAM Region : 0x%016lx - 0x%016lx [ 0x%016lx ]
{ %a }\n");
+
+ // PCIe MMIO32 Memory Space
+ VirtualMemoryTable[++Index].PhysicalBase = PcdGet32 (PcdPciMmio32Base);
+ VirtualMemoryTable[Index].VirtualBase = PcdGet32 (PcdPciMmio32Base);
+ VirtualMemoryTable[Index].Length = (PcdGet32 (PcdPciMmio32Size) +
+ PcdGet32 (PcdPciIoSize));
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+ LOG_MEM ("PCIe MMIO32 & IO Region : 0x%016lx - 0x%016lx [ 0x%016lx ]
{ %a }\n");
+
+ // PCIe MMIO64 Memory Space
+ VirtualMemoryTable[++Index].PhysicalBase = PcdGet64 (PcdPciMmio64Base);
+ VirtualMemoryTable[Index].VirtualBase = PcdGet64 (PcdPciMmio64Base);
+ VirtualMemoryTable[Index].Length = PcdGet64 (PcdPciMmio64Size);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+ LOG_MEM ("PCIe MMIO64 Region : 0x%016lx - 0x%016lx [ 0x%016lx ]
{ %a }\n");
+
+ // CCIX ECAM Configuration Space
+ VirtualMemoryTable[++Index].PhysicalBase = PcdGet64
(PcdCcixExpressBaseAddress);
+ VirtualMemoryTable[Index].VirtualBase = PcdGet64
(PcdCcixExpressBaseAddress);
+ VirtualMemoryTable[Index].Length = (FixedPcdGet32 (PcdCcixBusMax) -
+ FixedPcdGet32 (PcdCcixBusMin) + 1) *
+ SIZE_1MB;
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+ LOG_MEM ("CCIX ECAM Region : 0x%016lx - 0x%016lx [ 0x%016lx ]
{ %a }\n");
+
+ // CCIX MMIO32 Memory Space
+ VirtualMemoryTable[++Index].PhysicalBase = PcdGet32 (PcdCcixMmio32Base);
+ VirtualMemoryTable[Index].VirtualBase = PcdGet32 (PcdCcixMmio32Base);
+ VirtualMemoryTable[Index].Length = (PcdGet32 (PcdCcixMmio32Size) +
+ PcdGet32 (PcdCcixIoSize));
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+ LOG_MEM ("CCIX MMIO32 & IO Region : 0x%016lx - 0x%016lx [ 0x%016lx ]
{ %a }\n");
+
+ // CCIX MMIO64 Memory Space
+ VirtualMemoryTable[++Index].PhysicalBase = PcdGet64 (PcdCcixMmio64Base);
+ VirtualMemoryTable[Index].VirtualBase = PcdGet64 (PcdCcixMmio64Base);
+ VirtualMemoryTable[Index].Length = PcdGet64 (PcdCcixMmio64Size);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+ LOG_MEM ("CCIX MMIO64 Region : 0x%016lx - 0x%016lx [ 0x%016lx ]
{ %a }\n");
+
// End of Table
VirtualMemoryTable[++Index].PhysicalBase = 0;
VirtualMemoryTable[Index].VirtualBase = 0;
--
2.17.1
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