Signed-off-by: Abner Chang <abner.ch...@hpe.com>
Cc: Daniel Schaefer <daniel.schae...@hpe.com>
Cc: Sunil V L <suni...@ventanamicro.com>
---
.../DeviceTree/U500DeviceTree.inf | 25 ++
.../FreedomU500VC707Board/DeviceTree/gpio.h | 45 +++
.../DeviceTree/sifive-fu500-prci.h | 19 ++
.../DeviceTree/fu500-c000.dtsi | 276 ++++++++++++++++++
.../DeviceTree/hifive-unleashed-a00.dts | 108 +++++++
5 files changed, 473 insertions(+)
create mode 100644
Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/DeviceTree/U500DeviceTree.inf
create mode 100644
Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/DeviceTree/gpio.h
create mode 100644
Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/DeviceTree/sifive-fu500-prci.h
create mode 100644
Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/DeviceTree/fu500-c000.dtsi
create mode 100644
Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/DeviceTree/hifive-unleashed-a00.dts
diff --git
a/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/DeviceTree/U500DeviceTree.inf
b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/DeviceTree/U500DeviceTree.inf
new file mode 100644
index 0000000000..3eeb8c51f4
--- /dev/null
+++
b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/DeviceTree/U500DeviceTree.inf
@@ -0,0 +1,25 @@
+## @file
+#
+# Device tree description of SiFive U500 VC707 platform
+#
+# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights
reserved.
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001A
+ BASE_NAME = U500DeviceTree
+ FILE_GUID = 25462CDA-221F-47DF-AC1D-259CFAA4E326 #
gDtPlatformDefaultDtbFileGuid
+ MODULE_TYPE = USER_DEFINED
+ VERSION_STRING = 1.0
+
+[Sources]
+ gpio.h
+ hifive-unleashed-a00.dts
+ fu500-c000.dtsi
+ sifive-fu500-prci.h
+
+[Packages]
+ MdePkg/MdePkg.dec
diff --git
a/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/DeviceTree/gpio.h
b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/DeviceTree/gpio.h
new file mode 100644
index 0000000000..bc7e2fe7a1
--- /dev/null
+++ b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/DeviceTree/gpio.h
@@ -0,0 +1,45 @@
+/** @file
+ This header provides constants for most GPIO bindings.
+
+ Most GPIO bindings include a flags cell as part of the GPIO specifier.
+ In most cases, the format of the flags cell uses the standard values
+ defined in this header.
+
+ Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights
reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef DT_BINDINGS_GPIO_GPIO_H_
+#define DT_BINDINGS_GPIO_GPIO_H_
+
+/* Bit 0 express polarity */
+#define GPIO_ACTIVE_HIGH 0
+#define GPIO_ACTIVE_LOW 1
+
+/* Bit 1 express single-endedness */
+#define GPIO_PUSH_PULL 0
+#define GPIO_SINGLE_ENDED 2
+
+/* Bit 2 express Open drain or open source */
+#define GPIO_LINE_OPEN_SOURCE 0
+#define GPIO_LINE_OPEN_DRAIN 4
+
+//
+// Open Drain/Collector is the combination of single-ended open drain
interface.
+// Open Source/Emitter is the combination of single-ended open source
interface.
+//
+#define GPIO_OPEN_DRAIN (GPIO_SINGLE_ENDED | GPIO_LINE_OPEN_DRAIN)
+#define GPIO_OPEN_SOURCE (GPIO_SINGLE_ENDED | GPIO_LINE_OPEN_SOURCE)
+
+/* Bit 3 express GPIO suspend/resume and reset persistence */
+#define GPIO_PERSISTENT 0
+#define GPIO_TRANSITORY 8
+
+/* Bit 4 express pull up */
+#define GPIO_PULL_UP 16
+
+/* Bit 5 express pull down */
+#define GPIO_PULL_DOWN 32
+
+#endif
diff --git
a/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/DeviceTree/sifive-fu500-prci.h
b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/DeviceTree/sifive-fu500-prci.h
new file mode 100644
index 0000000000..7efa0006a0
--- /dev/null
+++
b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/DeviceTree/sifive-fu500-prci.h
@@ -0,0 +1,19 @@
+/**@file
+
+ SPDX-License-Identifier: (GPL-2.0 OR MIT)
+ Copyright (c) 2018-2019 SiFive, Inc
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#ifndef __DT_BINDINGS_CLOCK_SIFIVE_FU500_PRCI_H
+#define __DT_BINDINGS_CLOCK_SIFIVE_FU500_PRCI_H
+
+/* Clock indexes for use by Device Tree data and the PRCI driver */
+
+#define PRCI_CLK_COREPLL 0
+#define PRCI_CLK_DDRPLL 1
+#define PRCI_CLK_GEMGXLPLL 2
+#define PRCI_CLK_TLCLK 3
+
+#endif
diff --git
a/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/DeviceTree/fu500-c000.dtsi
b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/DeviceTree/fu500-c000.dtsi
new file mode 100644
index 0000000000..82f10e71e0
--- /dev/null
+++
b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/DeviceTree/fu500-c000.dtsi
@@ -0,0 +1,276 @@
+/**@file
+ U500 VC707 Device Tree, compatible with fu540-c000 platform.
+
+ SPDX-License-Identifier: (GPL-2.0 OR MIT)
+ Copyright (c) 2018-2019 SiFive, Inc
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+/dts-v1/;
+
+#include "sifive-fu500-prci.h"
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "sifive,fu540-c000", "sifive,fu540";
+
+ aliases {
+ serial0 = &uart0;
+ ethernet0 = ð0;
+ };
+
+ chosen {
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cpu0: cpu@0 {
+ compatible = "sifive,u54-mc", "sifive,rocket0",
"riscv";
+ d-cache-block-size = <64>;
+ d-cache-sets = <64>;
+ d-cache-size = <32768>;
+ d-tlb-sets = <1>;
+ d-tlb-size = <32>;
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <64>;
+ i-cache-size = <32768>;
+ i-tlb-sets = <1>;
+ i-tlb-size = <32>;
+ mmu-type = "riscv,sv39";
+ reg = <0>;
+ riscv,isa = "rv64imafdc";
+ tlb-split;
+ next-level-cache = <&l2cache>;
+ cpu0_intc: interrupt-controller {
+ #interrupt-cells = <1>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ };
+ };
+ cpu1: cpu@1 {
+ compatible = "sifive,u54-mc", "sifive,rocket0",
"riscv";
+ d-cache-block-size = <64>;
+ d-cache-sets = <64>;
+ d-cache-size = <32768>;
+ d-tlb-sets = <1>;
+ d-tlb-size = <32>;
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <64>;
+ i-cache-size = <32768>;
+ i-tlb-sets = <1>;
+ i-tlb-size = <32>;
+ mmu-type = "riscv,sv39";
+ reg = <1>;
+ riscv,isa = "rv64imafdc";
+ tlb-split;
+ next-level-cache = <&l2cache>;
+ cpu1_intc: interrupt-controller {
+ #interrupt-cells = <1>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ };
+ };
+ cpu2: cpu@2 {
+ compatible = "sifive,u54-mc", "sifive,rocket0",
"riscv";
+ d-cache-block-size = <64>;
+ d-cache-sets = <64>;
+ d-cache-size = <32768>;
+ d-tlb-sets = <1>;
+ d-tlb-size = <32>;
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <64>;
+ i-cache-size = <32768>;
+ i-tlb-sets = <1>;
+ i-tlb-size = <32>;
+ mmu-type = "riscv,sv39";
+ reg = <2>;
+ riscv,isa = "rv64imafdc";
+ tlb-split;
+ next-level-cache = <&l2cache>;
+ cpu2_intc: interrupt-controller {
+ #interrupt-cells = <1>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ };
+ };
+ cpu3: cpu@3 {
+ compatible = "sifive,u54-mc", "sifive,rocket0",
"riscv";
+ d-cache-block-size = <64>;
+ d-cache-sets = <64>;
+ d-cache-size = <32768>;
+ d-tlb-sets = <1>;
+ d-tlb-size = <32>;
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <64>;
+ i-cache-size = <32768>;
+ i-tlb-sets = <1>;
+ i-tlb-size = <32>;
+ mmu-type = "riscv,sv39";
+ reg = <3>;
+ riscv,isa = "rv64imafdc";
+ tlb-split;
+ next-level-cache = <&l2cache>;
+ cpu3_intc: interrupt-controller {
+ #interrupt-cells = <1>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ };
+ };
+ };
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "sifive,fu540-c000", "sifive,fu540", "simple-bus";
+ ranges;
+ plic0: interrupt-controller@c000000 {
+ #interrupt-cells = <1>;
+ compatible = "sifive,plic-1.0.0";
+ reg = <0x0 0xc000000 0x0 0x4000000>;
+ riscv,ndev = <53>;
+ interrupt-controller;
+ interrupts-extended = <
+ &cpu0_intc 0xffffffff &cpu0_intc 9
+ &cpu1_intc 0xffffffff &cpu1_intc 9
+ &cpu2_intc 0xffffffff &cpu2_intc 9
+ &cpu3_intc 0xffffffff &cpu3_intc 9>;
+ };
+ prci: clock-controller@10000000 {
+ compatible = "sifive,fu540-c000-prci";
+ reg = <0x0 0x10000000 0x0 0x1000>;
+ clocks = <&hfclk>, <&rtcclk>;
+ #clock-cells = <1>;
+ };
+ uart0: serial@54000000 {
+ compatible = "sifive,fu540-c000-uart", "sifive,uart0";
+ reg = <0x0 0x54000000 0x0 0x1000>;
+ interrupt-parent = <&plic0>;
+ interrupts = <4>;
+ clocks = <&prci PRCI_CLK_TLCLK>;
+ status = "disabled";
+ };
+ dma: dma@3000000 {
+ compatible = "sifive,fu540-c000-pdma";
+ reg = <0x0 0x3000000 0x0 0x8000>;
+ interrupt-parent = <&plic0>;
+ interrupts = <23 24 25 26 27 28 29 30>;
+ #dma-cells = <1>;
+ };
+ i2c0: i2c@10030000 {
+ compatible = "sifive,fu540-c000-i2c", "sifive,i2c0";
+ reg = <0x0 0x10030000 0x0 0x1000>;
+ interrupt-parent = <&plic0>;
+ interrupts = <50>;
+ clocks = <&prci PRCI_CLK_TLCLK>;
+ reg-shift = <2>;
+ reg-io-width = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+ qspi0: spi@10040000 {
+ compatible = "sifive,fu540-c000-spi", "sifive,spi0";
+ reg = <0x0 0x10040000 0x0 0x1000
+ 0x0 0x20000000 0x0 0x10000000>;
+ interrupt-parent = <&plic0>;
+ interrupts = <51>;
+ clocks = <&prci PRCI_CLK_TLCLK>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+ qspi1: spi@10041000 {
+ compatible = "sifive,fu540-c000-spi", "sifive,spi0";
+ reg = <0x0 0x10041000 0x0 0x1000
+ 0x0 0x30000000 0x0 0x10000000>;
+ interrupt-parent = <&plic0>;
+ interrupts = <52>;
+ clocks = <&prci PRCI_CLK_TLCLK>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+ qspi2: spi@10050000 {
+ compatible = "sifive,fu540-c000-spi", "sifive,spi0";
+ reg = <0x0 0x10050000 0x0 0x1000>;
+ interrupt-parent = <&plic0>;
+ interrupts = <6>;
+ clocks = <&prci PRCI_CLK_TLCLK>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+ eth0: ethernet@10090000 {
+ compatible = "sifive,fu540-c000-gem";
+ interrupt-parent = <&plic0>;
+ interrupts = <53>;
+ reg = <0x0 0x10090000 0x0 0x2000
+ 0x0 0x100a0000 0x0 0x1000>;
+ local-mac-address = [00 00 00 00 00 00];
+ clock-names = "pclk", "hclk";
+ clocks = <&prci PRCI_CLK_GEMGXLPLL>,
+ <&prci PRCI_CLK_GEMGXLPLL>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+ pwm0: pwm@10020000 {
+ compatible = "sifive,fu540-c000-pwm", "sifive,pwm0";
+ reg = <0x0 0x10020000 0x0 0x1000>;
+ interrupt-parent = <&plic0>;
+ interrupts = <42 43 44 45>;
+ clocks = <&prci PRCI_CLK_TLCLK>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+ pwm1: pwm@10021000 {
+ compatible = "sifive,fu540-c000-pwm", "sifive,pwm0";
+ reg = <0x0 0x10021000 0x0 0x1000>;
+ interrupt-parent = <&plic0>;
+ interrupts = <46 47 48 49>;
+ clocks = <&prci PRCI_CLK_TLCLK>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+ l2cache: cache-controller@2010000 {
+ compatible = "sifive,fu540-c000-ccache", "cache";
+ cache-block-size = <64>;
+ cache-level = <2>;
+ cache-sets = <1024>;
+ cache-size = <2097152>;
+ cache-unified;
+ interrupt-parent = <&plic0>;
+ interrupts = <1 2 3>;
+ reg = <0x0 0x2010000 0x0 0x1000>;
+ };
+ gpio: gpio@10060000 {
+ compatible = "sifive,fu540-c000-gpio", "sifive,gpio0";
+ interrupt-parent = <&plic0>;
+ interrupts = <7>, <8>, <9>, <10>, <11>, <12>, <13>,
+ <14>, <15>, <16>, <17>, <18>, <19>, <20>,
+ <21>, <22>;
+ reg = <0x0 0x10060000 0x0 0x1000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&prci PRCI_CLK_TLCLK>;
+ status = "disabled";
+ };
+ clint: clint@2000000 {
+ compatible = "riscv,clint0";
+ interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7
+ &cpu1_intc 3 &cpu1_intc 7
+ &cpu2_intc 3 &cpu2_intc 7
+ &cpu3_intc 3 &cpu3_intc 7>;
+ reg = <0x0 0x2000000 0x0 0xc0000>;
+ };
+ };
+};
diff --git
a/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/DeviceTree/hifive-unleashed-a00.dts
b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/DeviceTree/hifive-unleashed-a00.dts
new file mode 100644
index 0000000000..2074b18fa8
--- /dev/null
+++
b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/DeviceTree/hifive-unleashed-a00.dts
@@ -0,0 +1,108 @@
+/**@file
+ U500 VC707 Device Tree
+
+ SPDX-License-Identifier: (GPL-2.0 OR MIT)
+ Copyright (c) 2018-2019 SiFive, Inc
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "fu500-c000.dtsi"
+#include "gpio.h"
+
+/* Clock frequency (in Hz) of the PCB crystal for rtcclk */
+#define RTCCLK_FREQ 1000000
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ model = "SiFive HiFive Unleashed A00";
+ compatible = "sifive,hifive-unleashed-a00", "sifive,fu540-c000";
+
+ chosen {
+ stdout-path = "serial0";
+ };
+
+ cpus {
+ timebase-frequency = <RTCCLK_FREQ>;
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x0 0x80000000 0x2 0x00000000>;
+ };
+
+ soc {
+ };
+
+ hfclk: hfclk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <33333333>;
+ clock-output-names = "hfclk";
+ };
+
+ rtcclk: rtcclk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <RTCCLK_FREQ>;
+ clock-output-names = "rtcclk";
+ };
+ gpio-restart {
+ compatible = "gpio-restart";
+ gpios = <&gpio 10 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+};
+
+&qspi0 {
+ status = "okay";
+ flash@0 {
+ compatible = "issi,is25wp256", "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <50000000>;
+ m25p,fast-read;
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
+ };
+};
+
+&qspi2 {
+ status = "okay";
+ mmc@0 {
+ compatible = "mmc-spi-slot";
+ reg = <0>;
+ spi-max-frequency = <20000000>;
+ voltage-ranges = <3300 3300>;
+ disable-wp;
+ };
+};
+
+ð0 {
+ status = "okay";
+ phy-mode = "gmii";
+ phy-handle = <&phy0>;
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+};
+
+&pwm0 {
+ status = "okay";
+};
+
+&pwm1 {
+ status = "okay";
+};
+
+&gpio {
+ status = "okay";
+};
--
2.31.1
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