Incorporate with opensbi to create three firmware domains,
- Addjust the ROM layout.
- Boot firmware domain, which built with opensbi library as M-mode access only
region.
- Firmware domain which includes PEI and DXE regions, the
PMP attribute is readable, wriable and executable.
- EFI Variable region which is readable and writable.
Signed-off-by: Abner Chang <abner.ch...@hpe.com>
Cc: Daniel Schaefer <daniel.schae...@hpe.com>
Cc: Sunil V L <suni...@ventanamicro.com>
---
.../FreedomU500VC707Board/U500.fdf.inc | 73 ++++++++++++++-----
.../FreedomU500VC707Board/VarStore.fdf.inc | 6 +-
2 files changed, 57 insertions(+), 22 deletions(-)
diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.fdf.inc
b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.fdf.inc
index e88aee8c02..abfb013a92 100644
--- a/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.fdf.inc
+++ b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.fdf.inc
@@ -10,35 +10,70 @@
DEFINE BLOCK_SIZE = 0x1000
DEFINE FW_BASE_ADDRESS = 0x80000000
-DEFINE FW_SIZE = 0x00800000
-DEFINE FW_BLOCKS = 0x800
+DEFINE FW_SIZE = 0x00900000
+DEFINE FW_BLOCKS = 0x900
#
-# 0x000000-0x7DFFFF code
-# 0x7E0000-0x800000 variables
+# 0x000000-0x800000 code
+# 0x800000-0x818000 variables
#
DEFINE CODE_BASE_ADDRESS = 0x80000000
-DEFINE CODE_SIZE = 0x007E0000
-DEFINE CODE_BLOCKS = 0x7E0
+DEFINE CODE_SIZE = 0x00800000
+DEFINE CODE_BLOCKS = 0x800
DEFINE VARS_BLOCKS = 0x20
-DEFINE SECFV_OFFSET = 0x00000000
-DEFINE SECFV_SIZE = 0x00030000
-DEFINE PEIFV_OFFSET = 0x00030000
-DEFINE PEIFV_SIZE = 0x00080000
-DEFINE SCRATCH_OFFSET = 0x000b0000
-DEFINE SCRATCH_SIZE = 0x00010000
-DEFINE FVMAIN_OFFSET = 0x00100000 # Must be power of 2 for PMP setting
-DEFINE FVMAIN_SIZE = 0x0018C000
-DEFINE VARS_OFFSET = 0x007E0000
-DEFINE VARS_SIZE = 0x00020000
+#
+# SEC + opensbi library is the root FW domain.
+# The base address must be round up to log2.
+#
+DEFINE SECFV_OFFSET = 0x00000000
+DEFINE SECFV_SIZE = 0x00040000
+DEFINE ROOT_FW_DOMAIN_SIZE = $(SECFV_SIZE)
+
+#
+# Other FV regions are in the second FW domain.
+# The size of memory region must be power of 2.
+# The base address must be aligned with the size.
+#
+# FW memory region
+#
+DEFINE PEIFV_OFFSET = 0x00400000
+DEFINE PEIFV_SIZE = 0x00180000
+DEFINE FVMAIN_OFFSET = 0x00580000
+DEFINE FVMAIN_SIZE = 0x00280000
+
+#
+# EFI Variable memory region.
+# The total size of EFI Variable FD must include
+# all of sub regions of EFI Variable
+#
+DEFINE VARS_OFFSET = 0x00800000
+DEFINE VARS_SIZE = 0x00007000
+DEFINE VARS_FTW_WORKING_OFFSET = 0x00807000
+DEFINE VARS_FTW_WORKING_SIZE = 0x00001000
+DEFINE VARS_FTW_SPARE_OFFSET = 0x00808000
+DEFINE VARS_FTW_SPARE_SIZE = 0x00018000
+
+#
+# Scratch area memory region
+#
+DEFINE SCRATCH_OFFSET = 0x00840000
+DEFINE SCRATCH_SIZE = 0x00010000
+
+DEFINE FW_DOMAIN_SIZE = $(FVMAIN_OFFSET) + $(FVMAIN_SIZE) - $(PEIFV_OFFSET)
+DEFINE VARIABLE_FW_SIZE = $(VARS_FTW_SPARE_OFFSET) + $(VARS_FTW_SPARE_SIZE) -
$(VARS_OFFSET)
+
+SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRootFirmwareDomainBaseAddress =
$(CODE_BASE_ADDRESS) + $(SECFV_OFFSET)
+SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRootFirmwareDomainSize =
$(ROOT_FW_DOMAIN_SIZE)
+SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFirmwareDomainBaseAddress =
$(CODE_BASE_ADDRESS) + $(PEIFV_OFFSET)
+SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFirmwareDomainSize =
$(FW_DOMAIN_SIZE)
SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFdBaseAddress =
$(FW_BASE_ADDRESS) + $(VARS_OFFSET)
-SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFdSize = $(VARS_SIZE)
+SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFdSize =
$(VARS_SIZE) + $(VARS_FTW_WORKING_SIZE) + $(VARS_FTW_SPARE_SIZE)
SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFdBlockSize =
$(BLOCK_SIZE)
+SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFirmwareRegionBaseAddress =
$(CODE_BASE_ADDRESS) + $(VARS_OFFSET)
+SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFirmwareRegionSize =
$(VARIABLE_FW_SIZE)
-SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFwStartAddress =
$(CODE_BASE_ADDRESS)
-SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFwEndAddress = $(CODE_BASE_ADDRESS)
+ $(SECFV_SIZE) + $(PEIFV_SIZE) + $(SCRATCH_SIZE)
SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdOpenSbiStackSize = 8192
SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdScratchRamBase =
$(CODE_BASE_ADDRESS) + $(SCRATCH_OFFSET)
SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdScratchRamSize = $(SCRATCH_SIZE)
diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/VarStore.fdf.inc
b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/VarStore.fdf.inc
index c287bb4336..d7d75fa494 100644
--- a/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/VarStore.fdf.inc
+++ b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/VarStore.fdf.inc
@@ -9,7 +9,7 @@
#
##
-$(VARS_OFFSET)|0x00007000
+$(VARS_OFFSET)|$(VARS_SIZE)
gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPlatformFlashNvStorageVariableBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
#
# NV_VARIABLE_STORE
@@ -56,7 +56,7 @@ DATA = {
0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
}
-0x007e7000|0x00001000
+$(VARS_FTW_WORKING_OFFSET)|$(VARS_FTW_WORKING_SIZE)
gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPlatformFlashNvStorageFtwWorkingBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
#
#NV_FTW_WROK
@@ -72,7 +72,7 @@ DATA = {
0xE0, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
}
-0x007e8000|0x00018000
+$(VARS_FTW_SPARE_OFFSET)|$(VARS_FTW_SPARE_SIZE)
gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPlatformFlashNvStorageFtwSpareBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
#
#NV_FTW_SPARE
--
2.31.1
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