On 10/14/21 1:31 AM, Gerd Hoffmann wrote: > On Wed, Oct 13, 2021 at 11:56:58AM -0500, Brijesh Singh wrote: >> BZ: >> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fbugzilla.tianocore.org%2Fshow_bug.cgi%3Fid%3D3275&data=04%7C01%7Cbrijesh.singh%40amd.com%7C82e310da29774221b2e908d98eed0a57%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637697971033546009%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&sdata=bWQoR678mAGBOGXn2UO9NdyeQocUZjj7TnpmzWp9m5U%3D&reserved=0 >> >> The initial page built during the SEC phase is used by the >> MemEncryptSevSnpValidateSystemRam() for the system RAM validation. The >> page validation process requires using the PVALIDATE instruction; the >> instruction accepts a virtual address of the memory region that needs >> to be validated. If hardware encounters a page table walk failure (due >> to page-not-present) then it raises #GP. >> >> The initial page table built in SEC phase address up to 4GB. Add an >> internal function to extend the page table to cover > 4GB. The function >> builds 1GB entries in the page table for access > 4GB. This will provide >> the support to call PVALIDATE instruction for the virtual address > >> 4GB in PEI phase. > I think I asked this before: This is likewise temporary until the > memory core can track page state and ovmf can handle lazy > acceptance/validation of memory > 4G in DXE phase, correct? Yes, this should go away with Lazy validation. Ah, my bad I missed your request to document it. I will add the comment. > Can you add a comment for that? > > The code looks good. > > take care, > Gerd >
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