Hi, > > If we can use 4-level paging initially, then we surely should go for option > > (1) > > and simply not touch the reset vectors paging code.
> After PoC I find this option is not a good one. Though the reset > vectors is not touched, there are tricky changes in DxeIpl. To set up > 5-level paging in an 4-level paging, it should first be switched from > 64-bit long mode to 32 protected mode, then turn off the Paging, > disable IA32_ERER.LME, then set the Cr4. The tricky thing is that in > TDX IA32_EFER is not changeable. MdeModulePkg/.../DxeIpl is widely > used and it is high risk to make such changes. Ok. One more question: Do we have to use 5-level paging at all? The only reason I could see is accepting memory with a gpa above 4-level address space. But with the longer-term plan to support lazy acceptance (and passing unaccepted memory ranges to the guest kernel) this reason goes away. So I think we could just leave it to the guest kernel to deal with the switch from 4-level to 5-level paging. Or do I miss something? take care, Gerd -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#80476): https://edk2.groups.io/g/devel/message/80476 Mute This Topic: https://groups.io/mt/85242569/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
