On Fri, Sep 03, 2021 at 03:03:50AM +0000, Yao, Jiewen wrote:
> HI Min/Gerd
> I think we have multiple ways to enable 5 level paging.
> 
> 1) We do not change to 5 level in initial paging in reset vector.
> We can switch from 4 level to 5 level later when permanent memory is 
> available.
> We don't need change flash layout.

Does that work with tdx?

I had the impression that ovmf can't choose whenever it uses 4-level or
5-level paging in case tdx is enabled, but instead has to use what the
tdx firmware (or hardware?) dictates.  And this being the reason why we
have to deal with that in the reset vector in the first place.

But maybe I'm wrong here.

If we can use 4-level paging initially, then we surely should go for
option (1) and simply not touch the reset vectors paging code.

> 2) We can enable 5 level paging in initial paging.
> 2.1) We can enable 5 level paging with 1G paging support.
> We don't need change flash layout. Only 3 pages is needed. (12K)
> I don't know if we can real case that a CPU support 5 level but without 1G 
> paging.
> 
> 2.2) We can still enable 5 level paging with 2M paging.
> 2.2.1) We can change flash layout to increase 6 pages (24K) memory to 7 pages 
> (28K).
> So the CR3 in 5 level is same as the CR3 in 4 level.
> 
> 2.2.2) We don't change flash layout but steal another page in somewhere else 
> - PcdOvmfPml5Base
> That means CR3 in 5 level is different with CR4 in 4 level.
> Personally, I don't like the idea to create PcdOvmfPml5Base/Size
> Other AP MUST check 5 level and 4 level to get right CR3 location. That is 
> tricky and unnecessary.
> 
> In current patch, 2.2.2) is used.
> 
> I suggest we also evaluate option 1), 2.1) and 2.2.1).

My idea is 2.2.1 with a fixed, 5-level layout.
Then use 4-level-cr3 == 5-level-cr3 + PAGE_SIZE

2.1 looks good too.

take care,
  Gerd



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