The RD-N1-Edge dual-chip platform includes two RD-N1-Edge single-chip
platforms connected over cache coherent interconnect. Each of the
RD-N1-Edge single-chip platform includes two clusters with four
single-thread CPUs. Each of the CPUs include 64KB L1 Data cache, 64KB
L1 Instruction cache and 512KB L2 cache. Each cluster includes a 2MB
L3 cache. The platform also includes a system level cache of 8MB per
chip. Add PPTT table for RD-N1-Edge dual-chip platform with this
information.
Signed-off-by: Pranav Madhu <pranav.ma...@arm.com>
---
.../AcpiTables/RdN1EdgeX2AcpiTables.inf | 3 +-
.../SgiPkg/AcpiTables/RdN1EdgeX2/Pptt.aslc | 191 ++++++++++++++++++
2 files changed, 193 insertions(+), 1 deletion(-)
create mode 100644 Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Pptt.aslc
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2AcpiTables.inf
b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2AcpiTables.inf
index ba400de0454b..ebb77979606e 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2AcpiTables.inf
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2AcpiTables.inf
@@ -1,7 +1,7 @@
## @file
# ACPI table data and ASL sources required to boot the platform.
#
-# Copyright (c) 2020, ARM Ltd. All rights reserved.
+# Copyright (c) 2021, ARM Ltd. All rights reserved.
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -23,6 +23,7 @@
Mcfg.aslc
RdN1Edge/Dsdt.asl
RdN1EdgeX2/Madt.aslc
+ RdN1EdgeX2/Pptt.aslc
RdN1EdgeX2/Srat.aslc
Spcr.aslc
Ssdt.asl
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Pptt.aslc
b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Pptt.aslc
new file mode 100644
index 000000000000..3cdcd7714c1f
--- /dev/null
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Pptt.aslc
@@ -0,0 +1,191 @@
+/** @file
+* Processor Properties Topology Table (PPTT) for RD-N1-Edge dual-chip platform
+*
+* This file describes the topological structure of the processor block on the
+* RD-N1-Edge dual-chip platform in the form as defined by ACPI PPTT table. The
+* RD-N1-Edge dual-chip platform includes two RD-N1-Edge single-chip platforms
+* connected over cache coherent interconnect. Each of the RD-N1-Edge
single-chip
+* platform includes two clusters with four single-thread CPUS. Each of the CPUs
+* include 64KB L1 Data cache, 64KB L1 Instruction cache and 512KB L2 cache.
Each
+* cluster includes a 2MB L3 cache. Each instance of the chip includes a system
+* level cache of 8MB.
+*
+* Copyright (c) 2021, ARM Limited. All rights reserved.
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+* @par Specification Reference:
+* - ACPI 6.3, Chapter 5, Section 5.2.29, Processor Properties Topology Table
+**/
+
+#include <IndustryStandard/Acpi.h>
+#include <Library/AcpiLib.h>
+#include <Library/ArmLib.h>
+#include <Library/PcdLib.h>
+
+#include "SgiPlatform.h"
+#include "SgiAcpiHeader.h"
+
+#define CHIP_COUNT FixedPcdGet32 (PcdChipCount)
+
+#define PPTT_CORE_INIT(pid, cid, coreId)
\
+ {
\
+ /* Parameters for CPU Core */
\
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT (
\
+ __builtin_offsetof (RD_PPTT_CORE, DCache), /* Length */
\
+ PPTT_PROCESSOR_CORE_FLAGS, /* Flag */
\
+ __builtin_offsetof (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE,
\
+ Package[pid].Cluster[cid]), /* Parent */
\
+ ((pid << 3) | (cid << 2) | coreId), /* ACPI Id */
\
+ 2 /* Num of private resource
*/\
+ ),
\
+
\
+ /* Offsets of the private resources */
\
+ {
\
+ __builtin_offsetof (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE,
\
+ Package[pid].Cluster[cid].Core[coreId].DCache),
\
+ __builtin_offsetof (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE,
\
+ Package[pid].Cluster[cid].Core[coreId].ICache)
\
+ },
\
+
\
+ /* L1 Data Cache Parameters */
\
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT (
\
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */
\
+ __builtin_offsetof (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE,
\
+ Package[pid].Cluster[cid].Core[coreId].L2Cache),
\
+ /* Next level of cache */
\
+ SIZE_64KB, /* Size */
\
+ 256, /* Num of sets */
\
+ 4, /* Associativity */
\
+ PPTT_DATA_CACHE_ATTR, /* Attributes */
\
+ 64 /* Line size */
\
+ ),
\
+
\
+ /* L1 Instruction Cache Parameters */
\
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT (
\
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */
\
+ __builtin_offsetof (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE,
\
+ Package[pid].Cluster[cid].Core[coreId].L2Cache),
\
+ /* Next level of cache */
\
+ SIZE_64KB, /* Size */
\
+ 256, /* Num of sets */
\
+ 4, /* Associativity */
\
+ PPTT_INST_CACHE_ATTR, /* Attributes */
\
+ 64 /* Line size */
\
+ ),
\
+
\
+ /* L2 Cache Parameters */
\
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT (
\
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */
\
+ 0, /* Next level of cache */
\
+ SIZE_512KB, /* Size */
\
+ 1024, /* Num of sets */
\
+ 8, /* Associativity */
\
+ PPTT_UNIFIED_CACHE_ATTR, /* Attributes */
\
+ 64 /* Line size */
\
+ ),
\
+ }
+
+#define PPTT_CLUSTER_INIT(pid, cid)
\
+ {
\
+ /* Parameters for Cluster */
\
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT (
\
+ __builtin_offsetof (RD_PPTT_CLUSTER, L3Cache), /* Length */
\
+ PPTT_PROCESSOR_CLUSTER_FLAGS, /* Flag */
\
+ __builtin_offsetof (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE,
\
+ Package[pid]), /* Parent */
\
+ 0, /* ACPI Id */
\
+ 1 /* Num of private resource */
\
+ ),
\
+
\
+ /* Offsets of the private resources */
\
+ __builtin_offsetof (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE,
\
+ Package[pid].Cluster[cid].L3Cache),
\
+
\
+ /* L3 Cache Parameters */
\
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT (
\
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */
\
+ 0, /* Next level of cache */
\
+ SIZE_2MB, /* Size */
\
+ 2048, /* Num of sets */
\
+ 16, /* Associativity */
\
+ PPTT_UNIFIED_CACHE_ATTR, /* Attributes */
\
+ 64 /* Line size */
\
+ ),
\
+
\
+ {
\
+ PPTT_CORE_INIT (pid, cid, 0),
\
+ PPTT_CORE_INIT (pid, cid, 1),
\
+ PPTT_CORE_INIT (pid, cid, 2),
\
+ PPTT_CORE_INIT (pid, cid, 3)
\
+ }
\
+ }
+
+#define PPTT_PACKAGE_INIT(pid)
\
+ {
\
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT (
\
+ __builtin_offsetof (RDN1EDGEX2_PPTT_PACKAGE , Slc), /* Length */
\
+ PPTT_PROCESSOR_PACKAGE_FLAGS, /* Flag */
\
+ 0, /* Parent */
\
+ 0, /* ACPI Id */
\
+ 1 /* Num of private resource */
\
+ ),
\
+
\
+ /* Offsets of the private resources */
\
+ __builtin_offsetof (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE,
\
+ Package[pid].Slc),
\
+
\
+ /* SLC Parameters */
\
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT (
\
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */
\
+ 0, /* Next level of cache */
\
+ SIZE_8MB, /* Size */
\
+ 8192, /* Num of sets */
\
+ 16, /* Associativity */
\
+ PPTT_UNIFIED_CACHE_ATTR, /* Attributes */
\
+ 64 /* Line size */
\
+ ),
\
+
\
+ {
\
+ PPTT_CLUSTER_INIT (pid, 0),
\
+ PPTT_CLUSTER_INIT (pid, 1),
\
+ }
\
+ }
+
+#pragma pack(1)
+typedef struct {
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Package;
+ UINT32 Offset;
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE Slc;
+ RD_PPTT_CLUSTER Cluster[CLUSTER_COUNT];
+} RDN1EDGEX2_PPTT_PACKAGE;
+
+/*
+ * Processor Properties Topology Table
+ */
+typedef struct {
+ EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Header;
+ RDN1EDGEX2_PPTT_PACKAGE Package[CHIP_COUNT];
+} EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE;
+#pragma pack ()
+
+STATIC EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE Pptt = {
+ {
+ ARM_ACPI_HEADER (
+ EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE,
+ EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE,
+ EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION
+ )
+ },
+
+ {
+ PPTT_PACKAGE_INIT (0),
+ PPTT_PACKAGE_INIT (1)
+ }
+};
+
+/*
+ * Reference the table being generated to prevent the optimizer from removing
+ * the data structure from the executable
+ */
+VOID* CONST ReferenceAcpiTable = &Pptt;
--
2.17.1
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