The RD-V1 quad-chip platform consists of four chips connected over cache
coherent interconnect. Each chip on the platform includes four single-
thread CPUS. Each of the CPUs include 64KB L1 Data cache, 64KB L1
Instruction cache and 1MB L2 cache. The platform also includes a system
level cache of 16MB per chip. Add PPTT table for RD-V1 quad-chip
platform with this information.
Signed-off-by: Pranav Madhu <pranav.ma...@arm.com>
---
.../SgiPkg/AcpiTables/RdV1McAcpiTables.inf | 3 +-
.../ARM/SgiPkg/AcpiTables/RdV1Mc/Pptt.aslc | 172 ++++++++++++++++++
2 files changed, 174 insertions(+), 1 deletion(-)
create mode 100644 Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Pptt.aslc
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdV1McAcpiTables.inf
b/Platform/ARM/SgiPkg/AcpiTables/RdV1McAcpiTables.inf
index 08351b1e98e6..40fd6ae00270 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdV1McAcpiTables.inf
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdV1McAcpiTables.inf
@@ -1,7 +1,7 @@
## @file
# ACPI table data and ASL sources required to boot the platform.
#
-# Copyright (c) 2020, Arm Ltd. All rights reserved.
+# Copyright (c) 2020-2021, Arm Ltd. All rights reserved.
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -23,6 +23,7 @@
Mcfg.aslc
RdV1Mc/Dsdt.asl
RdV1Mc/Madt.aslc
+ RdV1Mc/Pptt.aslc
RdV1Mc/Srat.aslc
Spcr.aslc
Ssdt.asl
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Pptt.aslc
b/Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Pptt.aslc
new file mode 100644
index 000000000000..f5c7b0f61d94
--- /dev/null
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Pptt.aslc
@@ -0,0 +1,172 @@
+/** @file
+* Processor Properties Topology Table (PPTT) for RD-V1 quad-chip platform
+*
+* This file describes the topological structure of the processor block on the
+* RD-V1 quad-chip platform in the form as defined by ACPI PPTT table. The RD-V1
+* quad-chip platform is composed of four identical chips connected over cache
+* coherent interconnect. Each of the chip on the platform includes four single
+* thread CPUS. Each of the CPUs include 64KB L1 Data cache, 64KB L1 Instruction
+* cache and 1MB L2 cache. The platform also includes a system level cache of
+* 16MB per chip.
+*
+* Copyright (c) 2021, ARM Limited. All rights reserved.
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+* @par Specification Reference:
+* - ACPI 6.3, Chapter 5, Section 5.2.29, Processor Properties Topology Table
+**/
+
+#include <IndustryStandard/Acpi.h>
+#include <Library/AcpiLib.h>
+#include <Library/ArmLib.h>
+#include <Library/PcdLib.h>
+
+#include "SgiPlatform.h"
+#include "SgiAcpiHeader.h"
+
+#define CHIP_COUNT FixedPcdGet32 (PcdChipCount)
+
+#define PPTT_CORE_INIT(pid, cid, coreId)
\
+ {
\
+ /* Parameters for CPU Core */
\
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT (
\
+ __builtin_offsetof (RD_PPTT_CORE, DCache), /* Length */
\
+ PPTT_PROCESSOR_CORE_FLAGS, /* Flag */
\
+ __builtin_offsetof (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE,
\
+ Package[pid].Cluster[cid]), /* Parent */
\
+ ((pid << 2) | cid), /* ACPI Id */
\
+ 2 /* Num of private resource
*/\
+ ),
\
+
\
+ /* Offsets of the private resources */
\
+ {
\
+ __builtin_offsetof (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE,
\
+ Package[pid].Cluster[cid].Core[coreId].DCache),
\
+ __builtin_offsetof (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE,
\
+ Package[pid].Cluster[cid].Core[coreId].ICache)
\
+ },
\
+
\
+ /* L1 Data cache Parameters */
\
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT (
\
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */
\
+ __builtin_offsetof (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE,
\
+ Package[pid].Cluster[cid].Core[coreId].L2Cache),
\
+ /* Next level of cache */
\
+ SIZE_64KB, /* Size */
\
+ 256, /* Num of sets */
\
+ 4, /* Associativity */
\
+ PPTT_DATA_CACHE_ATTR, /* Attributes */
\
+ 64 /* Line size */
\
+ ),
\
+
\
+ /* L1 Instruction cache Parameters */
\
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT (
\
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */
\
+ __builtin_offsetof (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE,
\
+ Package[pid].Cluster[cid].Core[coreId].L2Cache),
\
+ /* Next level of cache */
\
+ SIZE_64KB, /* Size */
\
+ 256, /* Num of sets */
\
+ 4, /* Associativity */
\
+ PPTT_INST_CACHE_ATTR, /* Attributes */
\
+ 64 /* Line size */
\
+ ),
\
+
\
+ /* L2 Cache Parameters */
\
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT (
\
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */
\
+ 0, /* Next level of cache */
\
+ SIZE_1MB, /* Size */
\
+ 2048, /* Num of sets */
\
+ 8, /* Associativity */
\
+ PPTT_UNIFIED_CACHE_ATTR, /* Attributes */
\
+ 64 /* Line size */
\
+ ),
\
+ }
+
+#define PPTT_CLUSTER_INIT(pid, cid)
\
+ {
\
+ /* Parameters for Cluster */
\
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT (
\
+ __builtin_offsetof (RD_PPTT_MINIMAL_CLUSTER, Core), /* Length */
\
+ PPTT_PROCESSOR_CLUSTER_FLAGS, /* Flag */
\
+ __builtin_offsetof (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE,
\
+ Package[pid]), /* Parent */
\
+ 0, /* ACPI Id */
\
+ 0 /* Num of private resource */
\
+ ),
\
+
\
+ /* Offsets of the private resources */
\
+ __builtin_offsetof (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE,
\
+ Package[pid].Cluster[cid].Core),
\
+
\
+ {
\
+ PPTT_CORE_INIT (pid, cid, 0)
\
+ }
\
+ }
+
+#define PPTT_PACKAGE_INIT(pid)
\
+ {
\
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT (
\
+ __builtin_offsetof (RD_PPTT_SLC_PACKAGE, Slc), /* Length */
\
+ PPTT_PROCESSOR_PACKAGE_FLAGS, /* Flag */
\
+ 0, /* Parent */
\
+ 0, /* ACPI Id */
\
+ 1 /* Num of private resource
*/\
+ ),
\
+
\
+ /* Offsets of the private resources */
\
+ __builtin_offsetof (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE,
\
+ Package[pid].Slc),
\
+
\
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT (
\
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */
\
+ 0, /* Next level of cache */
\
+ SIZE_16MB, /* Size */
\
+ 16384, /* Num of sets */
\
+ 16, /* Associativity */
\
+ PPTT_UNIFIED_CACHE_ATTR, /* Attributes */
\
+ 64 /* Line size */
\
+ ),
\
+
\
+ {
\
+ PPTT_CLUSTER_INIT (pid, 0),
\
+ PPTT_CLUSTER_INIT (pid, 1),
\
+ PPTT_CLUSTER_INIT (pid, 2),
\
+ PPTT_CLUSTER_INIT (pid, 3),
\
+ }
\
+ }
+
+#pragma pack(1)
+/*
+ * Processor Properties Topology Table
+ */
+typedef struct {
+ EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Header;
+ RD_PPTT_SLC_PACKAGE Package[CHIP_COUNT];
+} EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE;
+#pragma pack ()
+
+STATIC EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE Pptt = {
+ {
+ ARM_ACPI_HEADER (
+ EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE,
+ EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE,
+ EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION
+ )
+ },
+
+ {
+ PPTT_PACKAGE_INIT (0),
+ PPTT_PACKAGE_INIT (1),
+ PPTT_PACKAGE_INIT (2),
+ PPTT_PACKAGE_INIT (3)
+ }
+};
+
+/*
+ * Reference the table being generated to prevent the optimizer from removing
+ * the data structure from the executable
+ */
+VOID* CONST ReferenceAcpiTable = &Pptt;
--
2.17.1
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