FVP Base Platform RevC is a configuration of the Base Platform that
includes a SMMUv3 and a PCIe subsystem. The PCIe subsystem has a
PCIe config region (ECAM) and two PCIe memory regions.
Add the SMMUv3 and PCIe config and memory regions to the memory map
so that the firmware can access and configure these components.
Signed-off-by: Sami Mujawar <sami.muja...@arm.com>
---
Platform/ARM/VExpressPkg/Include/Platform/RTSM/ArmPlatform.h | 6
+++-
Platform/ARM/VExpressPkg/Library/ArmVExpressLibRTSM/ArmVExpressLib.inf | 12
+++++++-
Platform/ARM/VExpressPkg/Library/ArmVExpressLibRTSM/RTSMMem.c | 31
++++++++++++++++++--
3 files changed, 45 insertions(+), 4 deletions(-)
diff --git a/Platform/ARM/VExpressPkg/Include/Platform/RTSM/ArmPlatform.h
b/Platform/ARM/VExpressPkg/Include/Platform/RTSM/ArmPlatform.h
index
499f62b2dc405c777e2266f4cbdaba963f5d26a2..96cc131dac91e428881f2506d277222490b649cb
100644
--- a/Platform/ARM/VExpressPkg/Include/Platform/RTSM/ArmPlatform.h
+++ b/Platform/ARM/VExpressPkg/Include/Platform/RTSM/ArmPlatform.h
@@ -1,7 +1,7 @@
/** @file
* Header defining Versatile Express constants (Base addresses, sizes, flags)
*
-* Copyright (c) 2011, ARM Limited. All rights reserved.
+* Copyright (c) 2011 - 2021, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
*
@@ -73,4 +73,8 @@
#define SBSA_WATCHDOG_BASE 0x2a440000
#define SBSA_WATCHDOG_SIZE (2 * SIZE_64KB)
+// SMMUv3 - FVP RevC
+#define FVP_REVC_SMMUV3_BASE 0x2B400000
+#define FVP_REVC_SMMUV3_SIZE SIZE_1MB
+
#endif
diff --git
a/Platform/ARM/VExpressPkg/Library/ArmVExpressLibRTSM/ArmVExpressLib.inf
b/Platform/ARM/VExpressPkg/Library/ArmVExpressLibRTSM/ArmVExpressLib.inf
index
d3441b0852c67b697067191f6b46f3ac6dce7707..929dadc28a84cdb2ca6c6a733b75a5c352922112
100644
--- a/Platform/ARM/VExpressPkg/Library/ArmVExpressLibRTSM/ArmVExpressLib.inf
+++ b/Platform/ARM/VExpressPkg/Library/ArmVExpressLibRTSM/ArmVExpressLib.inf
@@ -1,5 +1,5 @@
#/* @file
-# Copyright (c) 2011-2018, ARM Limited. All rights reserved.
+# Copyright (c) 2011-2021, Arm Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -54,5 +54,15 @@ [FixedPcd]
gArmPlatformTokenSpaceGuid.PcdArmMaliDpBase
gArmPlatformTokenSpaceGuid.PcdArmMaliDpMemoryRegionLength
+ # PCI Configuration space
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseSize
+
+ gArmTokenSpaceGuid.PcdPciMmio32Base
+ gArmTokenSpaceGuid.PcdPciMmio32Size
+
+ gArmTokenSpaceGuid.PcdPciMmio64Base
+ gArmTokenSpaceGuid.PcdPciMmio64Size
+
[Ppis]
gArmMpCoreInfoPpiGuid
diff --git a/Platform/ARM/VExpressPkg/Library/ArmVExpressLibRTSM/RTSMMem.c
b/Platform/ARM/VExpressPkg/Library/ArmVExpressLibRTSM/RTSMMem.c
index
21ffd64fb6350608b661298e4f336493696081df..13f181834ba8a3a8225a18147cbdbbde3807eb53
100644
--- a/Platform/ARM/VExpressPkg/Library/ArmVExpressLibRTSM/RTSMMem.c
+++ b/Platform/ARM/VExpressPkg/Library/ArmVExpressLibRTSM/RTSMMem.c
@@ -1,6 +1,6 @@
/** @file
*
-* Copyright (c) 2011-2018, ARM Limited. All rights reserved.
+* Copyright (c) 2011-2021, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
*
@@ -17,7 +17,7 @@
#define DP_BASE_DESCRIPTOR ((FixedPcdGet64 (PcdArmMaliDpBase) != 0) ? 1 :
0)
// Number of Virtual Memory Map Descriptors
-#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS (10 + DP_BASE_DESCRIPTOR)
+#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS (14 + DP_BASE_DESCRIPTOR)
// DDR attributes
#define DDR_ATTRIBUTES_CACHED ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK
@@ -161,6 +161,33 @@ ArmPlatformGetVirtualMemoryMap (
VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
}
+ // Map the PCI configration and memory space if the platform is FVP RevC.
+ if ((SysId & ARM_FVP_SYS_ID_REV_MASK) == ARM_FVP_BASE_REVC_REV) {
+ // SMMUv3
+ VirtualMemoryTable[++Index].PhysicalBase = FVP_REVC_SMMUV3_BASE;
+ VirtualMemoryTable[Index].VirtualBase = FVP_REVC_SMMUV3_BASE;
+ VirtualMemoryTable[Index].Length = FVP_REVC_SMMUV3_SIZE;
+ VirtualMemoryTable[Index].Attributes =
ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+ // PCI Configuration Space
+ VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64
(PcdPciExpressBaseAddress);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64
(PcdPciExpressBaseAddress);
+ VirtualMemoryTable[Index].Length = FixedPcdGet64
(PcdPciExpressBaseSize);
+ VirtualMemoryTable[Index].Attributes =
ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+ // PCI Memory Space
+ VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet32
(PcdPciMmio32Base);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet32
(PcdPciMmio32Base);
+ VirtualMemoryTable[Index].Length = FixedPcdGet32
(PcdPciMmio32Size);
+ VirtualMemoryTable[Index].Attributes =
ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+ // 64-bit PCI Memory Space
+ VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64
(PcdPciMmio64Base);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64
(PcdPciMmio64Base);
+ VirtualMemoryTable[Index].Length = FixedPcdGet64
(PcdPciMmio64Size);
+ VirtualMemoryTable[Index].Attributes =
ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+ }
+
// Map sparse memory region if present
if (HasSparseMemory) {
VirtualMemoryTable[++Index].PhysicalBase = SparseMemoryBase;
--
'Guid(CE165669-3EF3-493F-B85D-6190EE5B9759)'
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