> -----Original Message-----
> From: Ard Biesheuvel <ard.biesheu...@arm.com>
> Sent: Friday, April 24, 2020 11:38 AM
> To: devel@edk2.groups.io; Wasim Khan <wasim.k...@nxp.com>; Ard
> Biesheuvel <ard.biesheu...@linaro.org>
> Cc: Varun Sethi <v.se...@nxp.com>; Wu, Hao A <hao.a...@intel.com>; Ni, Ray
> <ray...@intel.com>
> Subject: Re: [edk2-devel] [PATCH] MdeModulePkg/PciHostBridge: Update Mem
> and PMem Limit Checks
>
> On 4/24/20 6:35 AM, Wasim Khan via groups.io wrote:
> >
> >
> >> -----Original Message-----
> >> From: Ard Biesheuvel <ard.biesheu...@linaro.org>
> >> Sent: Friday, April 24, 2020 12:27 AM
> >> To: Wasim Khan <wasim.k...@nxp.com>
> >> Cc: edk2-devel-groups-io <devel@edk2.groups.io>; Varun Sethi
> >> <v.se...@nxp.com>; Wu, Hao A <hao.a...@intel.com>; Ni, Ray
> >> <ray...@intel.com>
> >> Subject: Re: [PATCH] MdeModulePkg/PciHostBridge: Update Mem and PMem
> >> Limit Checks
> >>
> >> On Thu, 23 Apr 2020 at 12:43, Wasim Khan <wasim.k...@nxp.com> wrote:
> >>>
> >>> With Address Translation Support, it is possible and also correct
> >>> that Mem and Pmem Limit cross the 4GB boundary.
> >>> Update the checks so that Mem/PMem Limit should not cross 4GB from
> >>> the Mem/PMem Base address.
> >>>
> >>> Signed-off-by: Wasim Khan <wasim.k...@nxp.com>
> >>> ---
> >>> MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c | 8 ++++----
> >>> 1 file changed, 4 insertions(+), 4 deletions(-)
> >>>
> >>> diff --git a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c
> >>> b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c
> >>> index d304fae..9cf7e98 100644
> >>> --- a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c
> >>> +++ b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c
> >>> @@ -117,8 +117,8 @@ CreateRootBridge (
> >>> // Make sure Mem and MemAbove4G apertures are valid
> >>> //
> >>> if (RESOURCE_VALID (&Bridge->Mem)) {
> >>> - ASSERT (Bridge->Mem.Limit < SIZE_4GB);
> >>> - if (Bridge->Mem.Limit >= SIZE_4GB) {
> >>> + ASSERT (Bridge->Mem.Limit < (Bridge->Mem.Base + SIZE_4GB));
> >>> + if (Bridge->Mem.Limit >= (Bridge->Mem.Base + SIZE_4GB)) {
> >>> return NULL;
> >>> }
> >>> }
> >>> @@ -129,8 +129,8 @@ CreateRootBridge (
> >>> }
> >>> }
> >>> if (RESOURCE_VALID (&Bridge->PMem)) {
> >>> - ASSERT (Bridge->PMem.Limit < SIZE_4GB);
> >>> - if (Bridge->PMem.Limit >= SIZE_4GB) {
> >>> + ASSERT (Bridge->PMem.Limit < (Bridge->PMem.Base + SIZE_4GB));
> >>> + if (Bridge->PMem.Limit >= (Bridge->PMem.Base + SIZE_4GB)) {
> >>> return NULL;
> >>> }
> >>> }
> >>> --
> >>> 2.7.4
> >>>
> >>
> >> This is not the right fix.
> >>
> >> The translation offset should be taken into account for these checks
> >
> > Thanks for the review Ard.
> > device address = host address + translation offset.
> > Mem and Pmem represents "device address" , so that are already taking
> translation offset into account.
> >
>
> OK, apparently I am missing something.
>
> For the MMIO32 window, the limit has to be < 4 GB, since the whole region
> needs to be 32-bit addressable. Otherwise, how are you going to allocate a 32-
> bit BAR from the part of the window that is > 4 GB ?
>
OK, it is correct that we can not allocate 32-bit BAR from the part of window
that is > 4GB.
Thanks for catching it.
Thanks Ard, Ray for the good discussion.
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