> -----Original Message-----
> From: Wasim Khan <wasim.k...@nxp.com>
> Sent: Thursday, April 23, 2020 10:54 PM
> To: devel@edk2.groups.io; Ni, Ray <ray...@intel.com>
> Cc: ard.biesheu...@linaro.org; Varun Sethi <v.se...@nxp.com>; Wu, Hao A
> <hao.a...@intel.com>
> Subject: RE: [edk2-devel] [PATCH] MdeModulePkg/PciHostBridge: Update Mem and
> PMem Limit Checks
> > > >
> > > > Thanks for fixing the check.
> > > >
> > > > PCI_ROOT_BRIDGE_APERTURE.Base/Limit are device address while the
> > > > memory space in GCD belongs to host domain.
> > > > So, host address for Mem/Pmem should be below 4GB while device
> > > > address can across 4GB.
> > > >
> > >
> > >
> > > Hi Ray,
> > > Thank you for the review.
> > > There are cases when we don't have PCIe host address below 4GB, and
> > > the PCIe HOST Address space is only available above 4GB.
> > > For Example, Mem: 40000000 - FFFFFFFF Translation=FFFFFF6000000000
> > > will result in HOST Address = 0xA0FFFFFFFF . This is a valid use case,
> > > but below
> > check will report ASSERT for this HOST ADDRESS.
> >
> > OK. Now I remember that "Mem" reports the 32bit memory space (device
> > address) and "MemAbove4GB" reports the 64bit memory space (device address).
> >
> > Then if "Mem" reports memory range that across 4GB, it means the range above
> > 4GB should be reported through "MemAbove4GB".
> >
> Yes this is true, but some devices needs MMIO 32bit space only as per their
> BAR property, including E1000 EP.
I understand some devices contain only 32bit MMIO BAR so only 32bit memory
space (device address) can be assigned to them.
Can you tell me the value of Mem/MemAbove4GB/Pmem/PmemAbove4GB in your real
case?
Can you also tell me the PCI(e) device BAR information you want to initialize
through the EDKII PCI stack?
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