All the PCIe capability structures with the PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER; that has variable length features have been implemented in this way. I am counting around 12 structures which have been defined in the same way.
> -----Original Message----- > From: Ni, Ray <ray...@intel.com> > Sent: Thursday, March 19, 2020 2:30 PM > To: Javeed, Ashraf <ashraf.jav...@intel.com>; Gao, Liming > <liming....@intel.com>; Liu, Zhiguang <zhiguang....@intel.com>; Kinney, > Michael D <michael.d.kin...@intel.com> > Cc: devel@edk2.groups.io > Subject: RE: [edk2-devel] [PATCH V2] MdePkg-PciExpress40.h: DVSEC > definition missing > > I am sorry I just noticed this patch. > Is it better to have "DesignatedVendorSpecific[0]"? > This will make the sizeof (structure) more accurate. > > > -----Original Message----- > > From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of > Javeed, > > Ashraf > > Sent: Tuesday, March 17, 2020 4:04 PM > > To: devel@edk2.groups.io > > Cc: Kinney, Michael D <michael.d.kin...@intel.com>; Gao, Liming > > <liming....@intel.com>; Liu, Zhiguang <zhiguang....@intel.com> > > Subject: [edk2-devel] [PATCH V2] MdePkg-PciExpress40.h: DVSEC > > definition missing > > > > BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2598 > > > > All registers definition of DVSEC are defined as per the PCI Express > > Base Specification 4.0 chapter 7.9.6. > > > > Signed-off-by: Ashraf Javeed <ashraf.jav...@intel.com> > > Cc: Michael D Kinney <michael.d.kin...@intel.com> > > Cc: Liming Gao <liming....@intel.com> > > Cc: Zhiguang Liu <zhiguang....@intel.com> > > > > V2: fixed the comment section description for DVSEC definitions > > --- > > MdePkg/Include/IndustryStandard/PciExpress40.h | 28 > > ++++++++++++++++++++++++++++ > > 1 file changed, 28 insertions(+) > > > > diff --git a/MdePkg/Include/IndustryStandard/PciExpress40.h > > b/MdePkg/Include/IndustryStandard/PciExpress40.h > > index 9d9b272546..0564d72861 100644 > > --- a/MdePkg/Include/IndustryStandard/PciExpress40.h > > +++ b/MdePkg/Include/IndustryStandard/PciExpress40.h > > @@ -4,6 +4,7 @@ Support for the PCI Express 4.0 standard. > > This header file may not define all structures. Please extend as required. > > > > Copyright (c) 2018, American Megatrends, Inc. All rights > > reserved.<BR> > > +Copyright (c) 2020, Intel Corporation. All rights reserved.<BR> > > SPDX-License-Identifier: BSD-2-Clause-Patent > > > > **/ > > @@ -78,6 +79,33 @@ typedef struct { > > } PCI_EXPRESS_EXTENDED_CAPABILITIES_PHYSICAL_LAYER_16_0; > > ///@} > > > > +/// The Designated Vendor Specific Capability definitions /// Based > > +on section 7.9.6 of PCI Express Base Specification 4.0. > > +///@{ > > +typedef union { > > + struct { > > + UINT32 DvsecVendorId : 16; > > //bit 0..15 > > + UINT32 DvsecRevision : 4; > > //bit 16..19 > > + UINT32 DvsecLength : 12; > > //bit 20..31 > > + }Bits; > > + UINT32 Uint32; > > +}PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_1; > > + > > +typedef union { > > + struct { > > + UINT16 DvsecId : 16; > > //bit 0..15 > > + }Bits; > > + UINT16 Uint16; > > +}PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_2; > > + > > +typedef struct { > > + PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header; > > + PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_1 > > DesignatedVendorSpecificHeader1; > > + PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_2 > > DesignatedVendorSpecificHeader2; > > + UINT8 > > DesignatedVendorSpecific[1]; > > > +}PCI_EXPRESS_EXTENDED_CAPABILITIES_DESIGNATED_VENDOR_SPECIFIC; > > +///@} > > + > > #pragma pack() > > > > #endif > > -- > > 2.21.0.windows.1 > > > > > > -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#55989): https://edk2.groups.io/g/devel/message/55989 Mute This Topic: https://groups.io/mt/72019653/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
