Hi Ard, On 2019.12.19 13:12, Ard Biesheuvel wrote:
Hi Pete,On Thu, 19 Dec 2019 at 14:14, Pete Batard <p...@akeo.ie> wrote:From: Andrei Warkentin <andrey.warken...@gmail.com> Since the RPi4 PCIe host bridge is not ECAM compliant, we can not expose it as a host bridge to the OS via ACPI. However, given the hardwired nature of this platform, we can expose the xHCI controller that is guaranteed to live at the base of the MMIO32 BAR window as a platform device directly. It should be noted that the xHCI table is not finalized at this stage, as Windows xHCI support is still a major question mark. Signed-off-by: Pete Batard <p...@akeo.ie> --- Platform/RaspberryPi/RPi4/AcpiTables/AcpiTables.inf | 3 + Platform/RaspberryPi/RPi4/AcpiTables/Dsdt.asl | 1 + Platform/RaspberryPi/RPi4/AcpiTables/Xhci.asl | 137 ++++++++++++++++++++ 3 files changed, 141 insertions(+)...diff --git a/Platform/RaspberryPi/RPi4/AcpiTables/Xhci.asl b/Platform/RaspberryPi/RPi4/AcpiTables/Xhci.asl new file mode 100644 index 000000000000..e1fd501ab895 --- /dev/null +++ b/Platform/RaspberryPi/RPi4/AcpiTables/Xhci.asl @@ -0,0 +1,137 @@ +/** @file + * + * Copyright (c) 2019 Linaro, Limited. All rights reserved. + * Copyright (c) 2019 Andrei Warkentin <andrey.warken...@gmail.com> + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#include <IndustryStandard/Bcm2711.h> + +/* + * The following can be used to remove parenthesis from + * defined macros that the compiler complains about. + */ +#define ISOLATE_ARGS(...) __VA_ARGS__ +#define REMOVE_PARENTHESES(x) ISOLATE_ARGS x + +#define SANITIZED_PCIE_CPU_MMIO_WINDOW REMOVE_PARENTHESES(PCIE_CPU_MMIO_WINDOW) +#define SANITIZED_PCIE_REG_BASE REMOVE_PARENTHESES(PCIE_REG_BASE) + +/* + * According to UEFI boot log for the VLI device on Pi 4. + */ +#define XHCI_REG_LENGTH 0x1000 + +Device (SCB0) { + Name (_HID, "ACPI0004") + Name (_UID, 0x0) + Name (_CCA, 0x0) + + Method (_CRS, 0, Serialized) { // _CRS: Current Resource Settings + /* + * Container devices with _DMA must have _CRS, meaning SCB0 + * to provide all resources that XHC0 consumes (except + * interrupts). + */ + Name (RBUF, ResourceTemplate () { + QWordMemory (ResourceProducer, + , + MinFixed, + MaxFixed, + NonCacheable, + ReadWrite, + 0x0, + SANITIZED_PCIE_CPU_MMIO_WINDOW, // MIN + SANITIZED_PCIE_CPU_MMIO_WINDOW, // MAX + 0x0, + 0x1, // LEN + , + , + MMIO + ) + }) + CreateQwordField (RBUF, MMIO._MAX, MMBE) + CreateQwordField (RBUF, MMIO._LEN, MMLE) + Add (MMBE, XHCI_REG_LENGTH - 1, MMBE) + Add (MMLE, XHCI_REG_LENGTH - 1, MMLE) + Return (RBUF) + } + + Name (_DMA, ResourceTemplate() { + /* + * XHC0 is limited to DMA to first 3GB. Note this + * only applies to PCIe, not GENET or other devices + * next to the A72. + */ + QWordMemory (ResourceConsumer, + , + MinFixed, + MaxFixed, + NonCacheable, + ReadWrite, + 0x0, + 0x0, // MIN + 0xbfffffff, // MAX + 0x0, // TRA + 0xc0000000, // LEN + , + , + ) + }) + + Device (XHC0) + { + Name (_HID, "11063483") // _HID: Hardware IDI failed to spot this detail before. Even if MS appears to do so, I don't think it is OK to string random digits together to create hardware identifiers (and yes, I am aware it's the vendor and device IDs concatenated) What's wrong with using the below as the _HID?
Well, considering that we haven't managed to get Windows booting with xHCI yet anyway, and that this doesn't impact Linux boot (I've just validated this, to be safe), I see nothing wrong with using "PNP0D10" for now and then figure out later if there's a need to use something else.
If there are other requests leading to a v3, I'll apply that change. But if not, do you (or the person who's going to do it) mind changing the string during integration?
Regards, /Pete
+ Name (_CID, "PNP0D10") // _CID: Hardware ID + Name (_UID, 0x0) // _UID: Unique ID + Name (_CCA, 0x0) // _CCA: Cache Coherency Attribute + + Method (_CRS, 0, Serialized) { // _CRS: Current Resource Settings + Name (RBUF, ResourceTemplate () { + QWordMemory (ResourceConsumer, + , + MinFixed, + MaxFixed, + NonCacheable, + ReadWrite, + 0x0, + SANITIZED_PCIE_CPU_MMIO_WINDOW, // MIN + SANITIZED_PCIE_CPU_MMIO_WINDOW, // MAX + 0x0, + 0x1, // LEN + , + , + MMIO + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) { + 175 + } + }) + CreateQwordField (RBUF, MMIO._MAX, MMBE) + CreateQwordField (RBUF, MMIO._LEN, MMLE) + Add (MMBE, XHCI_REG_LENGTH - 1, MMBE) + Add (MMLE, XHCI_REG_LENGTH - 1, MMLE) + Return (RBUF) + } + + Method (_INI, 0, Serialized) { + OperationRegion (PCFG, SystemMemory, SANITIZED_PCIE_REG_BASE + PCIE_EXT_CFG_DATA, 0x1000) + Field (PCFG, AnyAcc, NoLock, Preserve) { + Offset (0), + VNID, 16, // Vendor ID + DVID, 16, // Device ID + CMND, 16, // Command register + STAT, 16, // Status register + } + + // Set command register to: + // 1) decode MMIO (set bit 1) + // 2) enable DMA (set bit 2) + // 3) enable interrupts (clear bit 10) + Debug = "xHCI enable" + Store (0x6, CMND) + } + } +} -- 2.21.0.windows.1
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