On Wed, Nov 27, 2019 at 19:44:37 +0100, Ard Biesheuvel wrote:
> Emit the cache topology into the device tree too when generating the
> CPU nodes and the cpu-map. Note that the cache geometries are all
> fixed and thus hardcoded - the only runtime variable aspect is how
> many L2 nodes to generate (one per detected cluster)
>
> Signed-off-by: Ard Biesheuvel <ard.biesheu...@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindh...@linaro.org>
> ---
> Silicon/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.c | 49
> ++++++++++++++++++++
> 1 file changed, 49 insertions(+)
>
> diff --git a/Silicon/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.c
> b/Silicon/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.c
> index 2f7b5e2a7b25..e723e77c7965 100644
> --- a/Silicon/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.c
> +++ b/Silicon/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.c
> @@ -305,6 +305,10 @@ PrepareFdt (
> UINT32 ClusterCount;
> UINT32 CoresInCluster;
> UINT32 ClusterId;
> + INT32 L2Node;
> + INT32 L3Node;
> + INT32 L2Phandle[NUM_CORES / 2];
> + INT32 L3Phandle;
> UINTN MpId;
> CHAR8 Name[10];
> AMD_MP_CORE_INFO_PROTOCOL *AmdMpCoreInfoProtocol;
> @@ -328,6 +332,42 @@ PrepareFdt (
> ASSERT (ArmCoreInfoTable != NULL);
> ASSERT (ArmCoreCount <= NUM_CORES);
>
> + // Create the L3 cache node
> + L3Node = fdt_add_subnode (Fdt, 0, "l3cache");
> + if (L3Node < 0) {
> + DEBUG ((DEBUG_ERROR, "FDT: Error creating 'l3cache' node\n"));
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + L3Phandle = fdt_alloc_phandle (Fdt);
> + fdt_setprop_cell (Fdt, L3Node, "cache-level", 3);
> + fdt_setprop_cell (Fdt, L3Node, "cache-size", SIZE_8MB);
> + fdt_setprop_cell (Fdt, L3Node, "cache-line-size", 64);
> + fdt_setprop_cell (Fdt, L3Node, "cache-sets", 8192);
> + fdt_setprop_empty (Fdt, L3Node, "cache-unified");
> + fdt_setprop_cell (Fdt, L3Node, "phandle", L3Phandle);
> +
> + ClusterCount = NumberOfClustersInTable (ArmCoreInfoTable, ArmCoreCount);
> + ASSERT (ClusterCount <= ARRAY_SIZE (L2Phandle));
> +
> + for (Index = 0; Index < ClusterCount; Index++) {
> + AsciiSPrint (Name, sizeof (Name), "l2cache%d", Index);
> +
> + L2Node = fdt_add_subnode (Fdt, 0, Name);
> + if (L2Node < 0) {
> + DEBUG ((DEBUG_ERROR, "FDT: Error creating '%a' node\n", Name));
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + L2Phandle[Index] = fdt_alloc_phandle (Fdt);
> + fdt_setprop_cell (Fdt, L2Node, "cache-size", SIZE_1MB);
> + fdt_setprop_cell (Fdt, L2Node, "cache-line-size", 64);
> + fdt_setprop_cell (Fdt, L2Node, "cache-sets", 1024);
> + fdt_setprop_empty (Fdt, L2Node, "cache-unified");
> + fdt_setprop_cell (Fdt, L2Node, "next-level-cache", L3Phandle);
> + fdt_setprop_cell (Fdt, L2Node, "phandle", L2Phandle[Index]);
> + }
> +
> // Get Id from primary CPU
> MpId = (UINTN)ArmReadMpidr ();
>
> @@ -367,6 +407,15 @@ PrepareFdt (
> fdt_setprop (Fdt, CpuNode, "reg", &MpId, sizeof (MpId));
> fdt_setprop_string (Fdt, CpuNode, "compatible", "arm,armv8");
> fdt_setprop_string (Fdt, CpuNode, "device_type", "cpu");
> +
> + fdt_setprop_cell (Fdt, CpuNode, "i-cache-size", 3 * SIZE_16KB);
> + fdt_setprop_cell (Fdt, CpuNode, "i-cache-line-size", 64);
> + fdt_setprop_cell (Fdt, CpuNode, "i-cache-sets", 256);
> + fdt_setprop_cell (Fdt, CpuNode, "d-cache-size", 2 * SIZE_16KB);
> + fdt_setprop_cell (Fdt, CpuNode, "d-cache-line-size", 64);
> + fdt_setprop_cell (Fdt, CpuNode, "d-cache-sets", 256);
> + fdt_setprop_cell (Fdt, CpuNode, "l2-cache",
> + L2Phandle[ArmCoreInfoTable[Index].ClusterId]);
> }
>
> // Create /cpu-map node
> --
> 2.17.1
>
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