Reviewed-by: Sai Chaganty <rangasai.v.chaga...@intel.com>
Minor feedback - The comments surrounding the new APIs (Early PCH Init) is not
matching with the API function name (EarlySiliconInit). It's good to keep them
consistent.
-----Original Message-----
From: Desimone, Nathaniel L
Sent: Wednesday, November 13, 2019 10:07 PM
To: devel@edk2.groups.io
Cc: Chiu, Chasel <chasel.c...@intel.com>; Kubacki, Michael A
<michael.a.kuba...@intel.com>; Chaganty, Rangasai V
<rangasai.v.chaga...@intel.com>
Subject: [edk2-platforms] [PATCH V1 05/13] CoffeelakeSiliconPkg: Add
SiliconInitLib
SiliconInitLib contains Silicon Init APIs that can be reused by BoardInitLib.
It is expected that several implementations of BoardInitLib exist for a given
SOC, these APIs allow the various BoardInitLib implementations to reuse common
silicon initialization code. This matches the implementation already found in
KabylakeSiliconPkg. This change also adds halting the TCO watch dog timer to
PEI, which was previously done in SEC.
Cc: Chasel Chiu <chasel.c...@intel.com>
Cc: Michael Kubacki <michael.a.kuba...@intel.com>
Cc: Sai Chaganty <rangasai.v.chaga...@intel.com>
Signed-off-by: Nate DeSimone <nathaniel.l.desim...@intel.com>
---
.../Include/Library/SiliconInitLib.h | 28 +++++
.../PeiSiliconInitLib/PeiSiliconInitLib.inf | 46 ++++++++
.../Library/PeiSiliconInitLib/SiliconInit.c | 19 +++
.../PeiSiliconInitLib/SiliconInitPreMem.c | 109 ++++++++++++++++++
4 files changed, 202 insertions(+)
create mode 100644
Silicon/Intel/CoffeelakeSiliconPkg/Include/Library/SiliconInitLib.h
create mode 100644
Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiliconInitLib/PeiSiliconInitLib.inf
create mode 100644
Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiliconInitLib/SiliconInit.c
create mode 100644
Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiliconInitLib/SiliconInitPreMem.c
diff --git
a/Silicon/Intel/CoffeelakeSiliconPkg/Include/Library/SiliconInitLib.h
b/Silicon/Intel/CoffeelakeSiliconPkg/Include/Library/SiliconInitLib.h
new file mode 100644
index 0000000000..a3411126a7
--- /dev/null
+++ b/Silicon/Intel/CoffeelakeSiliconPkg/Include/Library/SiliconInitLib.
+++ h
@@ -0,0 +1,28 @@
+/** @file++Copyright (c) 2019, Intel Corporation. All rights
+reserved.<BR>+SPDX-License-Identifier:
+BSD-2-Clause-Patent++**/++#ifndef _SILICON_INIT_LIB_H_+#define
+_SILICON_INIT_LIB_H_++#include <PiPei.h>++VOID+EarlySiliconInit (+
+VOID+ );++VOID+SiliconInit (+ VOID+ );++VOID+LateSiliconInit (+
+VOID+ );++#endif
\ No newline at end of file
diff --git
a/Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiliconInitLib/PeiSiliconInitLib.inf
b/Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiliconInitLib/PeiSiliconInitLib.inf
new file mode 100644
index 0000000000..47da5f608b
--- /dev/null
+++ b/Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiliconInitLib/PeiSi
+++ liconInitLib.inf
@@ -0,0 +1,46 @@
+### @file+#+# Copyright (c) 2019, Intel Corporation. All rights
reserved.<BR>+#+# SPDX-License-Identifier:
BSD-2-Clause-Patent+#+###++[Defines]+ INF_VERSION =
0x00010017+ BASE_NAME = SiliconInitLib+ FILE_GUID
= 82F2ACF0-2EBE-48C8-AC58-9D0F8BC1E16E+ VERSION_STRING
= 1.0+ MODULE_TYPE = PEIM+ LIBRARY_CLASS
= SiliconInitLib+#+# The following information is for reference only and
not required by the build tools.+#+# VALID_ARCHITECTURES = IA32 X64 IPF
EBC+#++[LibraryClasses]+ BaseLib+ BaseMemoryLib+ DebugLib+ HobLib+ IoLib+
PcdLib+ PeiServicesLib+ PchCycleDecodingLib+ PmcLib++[Packages]+
MdePkg/MdePkg.dec+ CoffeelakeSiliconPkg/SiPkg.dec++[Sources]+ SiliconInit.c+
SiliconInitPreMem.c++[Guids]+ gTcoWdtHobGuid ##
CONSUMES++[Pcd]+ gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress ## CONSUMES+
gSiPkgTokenSpaceGuid.PcdTcoBaseAddress ## CONSUMESdiff --git
a/Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiliconInitLib/SiliconInit.c
b/Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiliconInitLib/SiliconInit.c
new file mode 100644
index 0000000000..122c02a3e5
--- /dev/null
+++ b/Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiliconInitLib/Silic
+++ onInit.c
@@ -0,0 +1,19 @@
+/** @file+ Silicon Init APIs for MinPlatform BoardInitLib
+implementations.++Copyright (c) 2019, Intel Corporation. All rights
+reserved.<BR>+SPDX-License-Identifier:
+BSD-2-Clause-Patent++**/++#include <PiPei.h>++/**+ Late PCH
+Init+**/+VOID+LateSiliconInit (+ VOID+ )+{+}diff --git
+a/Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiliconInitLib/SiliconI
+nitPreMem.c
+b/Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiliconInitLib/SiliconI
+nitPreMem.c
new file mode 100644
index 0000000000..23e4a3d4a0
--- /dev/null
+++ b/Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiliconInitLib/Silic
+++ onInitPreMem.c
@@ -0,0 +1,109 @@
+/** @file+ Silicon Init APIs for MinPlatform BoardInitLib
implementations.++Copyright (c) 2019, Intel Corporation. All rights
reserved.<BR>+SPDX-License-Identifier: BSD-2-Clause-Patent++**/++#include
<PiPei.h>+#include <Guid/TcoWdtHob.h>+#include <Library/IoLib.h>+#include
<Library/DebugLib.h>+#include <Library/HobLib.h>+#include
<Library/PcdLib.h>+#include <Library/PeiServicesLib.h>+#include
<Library/PchCycleDecodingLib.h>+#include <Library/PmcLib.h>+#include
<Register/PchRegsLpc.h>+#include <Register/PchRegsPmc.h>++/**+ Early PCH
initialization+**/+VOID+EarlySiliconInit (+ VOID+ )+{+ UINT16 Data16;+
UINT8 Data8;+ UINT8 TcoRebootHappened;+ TCO_WDT_HOB
*TcoWdtHobPtr;+ EFI_STATUS Status;++ ///+ /// LPC I/O Configuration+ ///+
PchLpcIoDecodeRangesSet (+ (V_LPC_CFG_IOD_LPT_378 << N_LPC_CFG_IOD_LPT)
|+ (V_LPC_CFG_IOD_COMB_3E8 << N_LPC_CFG_IOD_COMB) |+
(V_LPC_CFG_IOD_COMA_3F8 << N_LPC_CFG_IOD_COMA)+ );++
PchLpcIoEnableDecodingSet (+ B_LPC_CFG_IOE_ME2 |+ B_LPC_CFG_IOE_SE |+
B_LPC_CFG_IOE_ME1 |+ B_LPC_CFG_IOE_KE |+ B_LPC_CFG_IOE_HGE |+
B_LPC_CFG_IOE_LGE |+ B_LPC_CFG_IOE_FDE |+ B_LPC_CFG_IOE_PPE |+
B_LPC_CFG_IOE_CBE |+ B_LPC_CFG_IOE_CAE+ );++ ///+ /// Halt the TCO
timer+ ///+ Data16 = IoRead16 (PcdGet16 (PcdTcoBaseAddress) +
R_TCO_IO_TCO1_CNT);+ Data16 |= B_TCO_IO_TCO1_CNT_TMR_HLT;+ IoWrite16
(PcdGet16 (PcdTcoBaseAddress) + R_TCO_IO_TCO1_CNT, Data16);++ ///+ /// Read
the Second TO status bit+ ///+ Data8 = IoRead8 (PcdGet16 (PcdTcoBaseAddress)
+ R_TCO_IO_TCO2_STS);+ if ((Data8 & B_TCO_IO_TCO2_STS_SECOND_TO) ==
B_TCO_IO_TCO2_STS_SECOND_TO) {+ TcoRebootHappened = 1;+ DEBUG
((DEBUG_INFO, "PlatformInitPreMem - TCO Second TO status bit is set. This might
be a TCO reboot\n"));+ }+ else {+ TcoRebootHappened = 0;+ }++ ///+ ///
Create HOB+ ///+ Status = PeiServicesCreateHob (EFI_HOB_TYPE_GUID_EXTENSION,
sizeof(TCO_WDT_HOB), (VOID **)&TcoWdtHobPtr);+ if (!EFI_ERROR (Status)) {+
TcoWdtHobPtr->Header.Name = gTcoWdtHobGuid;+ TcoWdtHobPtr->TcoRebootHappened
= TcoRebootHappened;+ }++ ///+ /// Clear the Second TO status bit+ ///+
IoWrite8 (PcdGet16 (PcdTcoBaseAddress) + R_TCO_IO_TCO2_STS,
B_TCO_IO_TCO2_STS_SECOND_TO);+}++/**+ Initialize the GPIO IO selection, GPIO
USE selection, and GPIO signal inversion registers++**/+VOID+SiliconInit (+
VOID+ )+{+ UINT16 ABase;++ ABase = PmcGetAcpiBase ();++ ///+ ///
Clear all pending SMI. On S3 clear power button enable so it will not generate
an SMI.+ ///+ IoWrite16 (ABase + R_ACPI_IO_PM1_EN, 0);+ IoWrite32 (ABase +
R_ACPI_IO_GPE0_EN_127_96, 0);+}--
2.23.0.windows.1
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