This patch adjusts the top device tree for the CN9131 development board
(variant A), based on the sources which are common for the Cn913x SoCs.
Also an .inf file is added to allow its compilation.
Signed-off-by: Marcin Wojtas <m...@semihalf.com>
---
Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9131DbA.inf | 22 +++++++++++++++++
Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-db.dtsi | 26
+++++++++++---------
2 files changed, 36 insertions(+), 12 deletions(-)
create mode 100644 Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9131DbA.inf
diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9131DbA.inf
b/Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9131DbA.inf
new file mode 100644
index 0000000..8108197
--- /dev/null
+++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/Cn9131DbA.inf
@@ -0,0 +1,22 @@
+## @file
+#
+# Device tree description of the Marvell CN9130-DB-A platform
+#
+# Copyright (c) 2019, Marvell International Ltd. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001B
+ BASE_NAME = Cn9131DbADeviceTree
+ FILE_GUID = 25462CDA-221F-47DF-AC1D-259CFAA4E326 #
gDtPlatformDefaultDtbFileGuid
+ MODULE_TYPE = USER_DEFINED
+ VERSION_STRING = 1.0
+
+[Sources]
+ cn9131-db-A.dts
+
+[Packages]
+ MdePkg/MdePkg.dec
diff --git a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-db.dtsi
b/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-db.dtsi
index c8e425a..9c9dfb6 100644
--- a/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-db.dtsi
+++ b/Silicon/Marvell/OcteonTx/DeviceTree/T91/cn9131-db.dtsi
@@ -6,15 +6,23 @@
*/
#undef CP110_NUM
-#undef CP110_PCIE_MEM_SIZE
+#undef CP110_NAME
+#undef CP110_BASE
+#undef CP110_PCIE0_BASE
+#undef CP110_PCIE1_BASE
+#undef CP110_PCIE2_BASE
#undef CP110_PCIEx_CPU_MEM_BASE
-#undef CP110_PCIEx_BUS_MEM_BASE
+#undef CP110_PCIEx_MEM_BASE
/* CP110-1 Settings */
+#define CP110_NAME cp1
#define CP110_NUM 1
-#define CP110_PCIE_MEM_SIZE(iface) (0xf00000)
-#define CP110_PCIEx_CPU_MEM_BASE(iface) (0xe2000000 + (iface) *
0x1000000)
-#define CP110_PCIEx_BUS_MEM_BASE(iface)
(CP110_PCIEx_CPU_MEM_BASE(iface))
+#define CP110_BASE f4000000
+#define CP110_PCIE0_BASE f4600000
+#define CP110_PCIE1_BASE f4620000
+#define CP110_PCIE2_BASE f4640000
+#define CP110_PCIEx_CPU_MEM_BASE(iface) (0xe2000000 + (iface) * 0x1000000)
+#define CP110_PCIEx_MEM_BASE(iface) (CP110_PCIEx_CPU_MEM_BASE(iface))
#include "armada-cp110.dtsi"
@@ -93,12 +101,6 @@
&cp1_sata0 {
status = "okay";
- /* CON32 */
- sata-port@1 {
- status = "okay";
- /* Generic PHY, providing serdes lanes */
- phys = <&cp1_comphy5 1>;
- };
};
/* U24 */
@@ -138,7 +140,7 @@
&cp1_syscon0 {
cp1_pinctrl: pinctrl {
- compatible = "marvell,cp115-standalone-pinctrl";
+ compatible = "marvell,armada-7k-pinctrl";
cp1_i2c0_pins: cp1-i2c-pins-0 {
marvell,pins = "mpp37", "mpp38";
--
2.7.4
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